@Vengineerさんの https://twitter.com/Vengineer/status/1365533449113587713 でXilinx Vitis HLS LLVM 2020.2を見て進めてみました。
Xilinx Vitis HLS LLVM 2020.2は次のURLで紹介されています。
Clang＋pragmaがOpen Sourceになったということなんですね。
さっそく試してみましょう。
ちなみに私の環境はUbuntu 20.04LTSです。
まずはダウンロードします。
$ git clone https://github.com/Xilinx/HLSディレクトリの移動を忘れずに…
$ cd HLSまずはツールチェーン？コンパイラ？をビルドします。
$ cd llvm
$ ./build.sh私の環境では64GBのメモリをフルに使ってビルドしていました。
裏でChromやVivadoなんかしてようもんなら、メモリを使い果たしてビルドエラーしていました。
vitis_hls_examplesにサンプルがあるので試してみましょう。
<VITIS_HLS_2020.2_DIR>はVitis HLSをインストールしたディレクトリです。
$ cd vitis_hls_examples/override_llvm_flow_demo
$ sources <VITIS_HLS_2020.2_DIR>/settings64.sh
$ vitis_hls run_hls.tcl下記が実行結果です。
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /opt/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/opt/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'hidemi' on host 'saturn' (Linux_x86_64 version 5.8.0-44-generic) on Sun Mar 07 22:48:34 JST 2021
INFO: [HLS 200-10] On os Ubuntu 20.04.2 LTS
INFO: [HLS 200-10] In directory '/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo'
Sourcing Tcl script './run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj
INFO: [HLS 200-10] Opening and resetting project '/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj'.
WARNING: [HLS 200-40] No /home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1510] Running: add_files hls_example.cpp
INFO: [HLS 200-10] Adding design file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb hls_example.cpp
INFO: [HLS 200-10] Adding test bench file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: set_top example
INFO: [HLS 200-1510] Running: open_solution -reset solution1
INFO: [HLS 200-10] Creating and opening solution '/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part virtex7
INFO: [HLS 200-10] Setting target device to 'xc7v585t-ffg1761-2'
INFO: [HLS 200-1510] Running: create_clock -period 300MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.333ns.
INFO: [HLS 200-1510] Running: csim_design
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../hls_example.cpp in debug mode
Generating csim.exe
Test passed.
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.5 seconds. CPU system time: 0.12 seconds. Elapsed time: 0.31 seconds; current allocated memory: 189.971 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 190.153 MB.
INFO: [HLS 200-10] Analyzing design file 'hls_example.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 13.15 seconds. CPU system time: 0.16 seconds. Elapsed time: 13.15 seconds; current allocated memory: 191.738 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
WARNING: [HLS 207-586] overriding the module target triple with fpga64-xilinx-none
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
INFO: [HLS 214-115] Multiple burst reads of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'a' (hls_example.cpp:31:20)
INFO: [HLS 214-115] Multiple burst writes of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'b' (hls_example.cpp:31:20)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 1.99 seconds. CPU system time: 0.14 seconds. Elapsed time: 2.12 seconds; current allocated memory: 192.790 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 192.792 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 194.585 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 194.757 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 215.907 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 208.554 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'example' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_31_1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'VITIS_LOOP_31_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 208.848 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 209.017 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/a' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/b' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on function 'example' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.02 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.02 seconds; current allocated memory: 209.946 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.57 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.58 seconds; current allocated memory: 217.825 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for example.
INFO: [VLOG 209-307] Generating Verilog RTL for example.
INFO: [HLS 200-1603] Design has MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 15.95 seconds. CPU system time: 0.32 seconds. Elapsed time: 16.1 seconds; current allocated memory: 218.428 MB.
INFO: [HLS 200-1510] Running: cosim_design
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
Build using "/opt/Xilinx/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling hls_example.cpp_pre.cpp.tb.cpp
Compiling apatb_example.cpp
Compiling apatb_example_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
Test passed.
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_example_top glbl -prj example.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_18 -L floating_point_v7_1_11 --lib ieee_proposed=./ieee_proposed -s example
Multi-threading is on. Using 14 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_a.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_a
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_b.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_b
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_example_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_b_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_b_m_axi
INFO: [VRFC 10-311] analyzing module example_b_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_b_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_b_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_b_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_b_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_b_m_axi_read
INFO: [VRFC 10-311] analyzing module example_b_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_a_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_a_m_axi
INFO: [VRFC 10-311] analyzing module example_a_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_a_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_a_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_a_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_a_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_a_m_axi_read
INFO: [VRFC 10-311] analyzing module example_a_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/dump_file_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_monitor.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_fifo_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/sample_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/sample_manager.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_process_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/csv_file_dump.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/dataflow_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [nodf_module_interface.sv:4]
INFO: [VRFC 10-311] analyzing module dataflow_monitor
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_process_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_fifo_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_dataflow_monitor_sv
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_a_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_a_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_a_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_b_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_b_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_b_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example
Compiling module xil_defaultlib.AESL_axi_master_a
Compiling module xil_defaultlib.AESL_axi_master_b
Compiling module xil_defaultlib.nodf_module_intf
Compiling module xil_defaultlib.dataflow_monitor_1
Compiling module xil_defaultlib.apatb_example_top
Compiling module work.glbl
Built simulation snapshot example
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/xsim.dir/example/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Sun Mar 7 22:49:02 2021...
****** xsim v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source xsim.dir/example/xsim_script.tcl
# xsim {example} -autoloadwcfg -tclbatch {example.tcl}
Vivado Simulator 2020.2
Time resolution is 1 ps
source example.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "109000"
// RTL Simulation : 1 / 1 [100.00%] @ "359000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 372410 ps : File "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.autotb.v" Line 462
## quit
INFO: [Common 17-206] Exiting xsim at Sun Mar 7 22:49:08 2021...
INFO: [COSIM 212-316] Starting C post checking ...
Test passed.
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 17.19 seconds. CPU system time: 0.73 seconds. Elapsed time: 17.29 seconds; current allocated memory: 222.565 MB.
INFO: [HLS 200-1510] Running: export_design -rtl verilog
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.
****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [Common 17-206] Exiting Vivado at Sun Mar 7 22:49:16 2021...
INFO: [HLS 200-802] Generated output file proj/solution1/impl/export.zip
INFO: [HLS 200-111] Finished Command export_design CPU user time: 8.76 seconds. CPU system time: 0.59 seconds. Elapsed time: 10.9 seconds; current allocated memory: 227.530 MB.
INFO: [HLS 200-112] Total CPU user time: 43.79 seconds. Total CPU system time: 2.02 seconds. Total elapsed time: 45.62 seconds; peak allocated memory: 217.825 MB.
INFO: [Common 17-206] Exiting vitis_hls at Sun Mar 7 22:49:19 2021...HLSの結果は次のようにVerilogHDLとかがで生成されました。
$ ls proj/solution1/syn/verilog/
example.v example_a_m_axi.v example_b_m_axi.v