@Vengineerさんの https://twitter.com/Vengineer/status/1365533449113587713 でXilinx Vitis HLS LLVM 2020.2を見て進めてみました。
Xilinx Vitis HLS LLVM 2020.2は次のURLで紹介されています。
Clang＋pragmaがOpen Sourceになったということなんですね。
さっそく試してみましょう。
ちなみに私の環境はUbuntu 20.04LTSです。
まずはダウンロードします。
$ git clone https://github.com/Xilinx/HLSディレクトリの移動を忘れずに…
$ cd HLSまずはツールチェーン？コンパイラ？をビルドします。
$ cd llvm
$ ./build.sh私の環境では64GBのメモリをフルに使ってビルドしていました。
裏でChromやVivadoなんかしてようもんなら、メモリを使い果たしてビルドエラーしていました。
vitis_hls_examplesにサンプルがあるので試してみましょう。
<VITIS_HLS_2020.2_DIR>はVitis HLSをインストールしたディレクトリです。
$ cd vitis_hls_examples/override_llvm_flow_demo
$ sources <VITIS_HLS_2020.2_DIR>/settings64.sh
$ vitis_hls run_hls.tcl下記が実行結果です。
****** Vitis HLS - High-Level Synthesis from C, C++ and OpenCL v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /opt/Xilinx/Vitis_HLS/2020.2/scripts/vitis_hls/hls.tcl -notrace
INFO: [HLS 200-10] Running '/opt/Xilinx/Vitis_HLS/2020.2/bin/unwrapped/lnx64.o/vitis_hls'
INFO: [HLS 200-10] For user 'hidemi' on host 'saturn' (Linux_x86_64 version 5.8.0-44-generic) on Sun Mar 07 22:48:34 JST 2021
INFO: [HLS 200-10] On os Ubuntu 20.04.2 LTS
INFO: [HLS 200-10] In directory '/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo'
Sourcing Tcl script './run_hls.tcl'
INFO: [HLS 200-1510] Running: open_project -reset proj
INFO: [HLS 200-10] Opening and resetting project '/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj'.
WARNING: [HLS 200-40] No /home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1510] Running: add_files hls_example.cpp
INFO: [HLS 200-10] Adding design file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: add_files -tb hls_example.cpp
INFO: [HLS 200-10] Adding test bench file 'hls_example.cpp' to the project
INFO: [HLS 200-1510] Running: set_top example
INFO: [HLS 200-1510] Running: open_solution -reset solution1
INFO: [HLS 200-10] Creating and opening solution '/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1'.
INFO: [HLS 200-10] Cleaning up the solution database.
WARNING: [HLS 200-40] No /home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/solution1.aps file found.
INFO: [HLS 200-1505] Using default flow_target 'vivado'
Resolution: For help on HLS 200-1505 see www.xilinx.com/cgi-bin/docs/rdoc?v=2020.2;t=hls+guidance;d=200-1505.html
INFO: [HLS 200-1510] Running: set_part virtex7
INFO: [HLS 200-10] Setting target device to 'xc7v585t-ffg1761-2'
INFO: [HLS 200-1510] Running: create_clock -period 300MHz
INFO: [SYN 201-201] Setting up clock 'default' with a period of 3.333ns.
INFO: [HLS 200-1510] Running: csim_design
INFO: [SIM 211-2] *************** CSIM start ***************
INFO: [SIM 211-4] CSIM will launch GCC as the compiler.
Compiling ../../../../hls_example.cpp in debug mode
Generating csim.exe
Test passed.
INFO: [SIM 211-1] CSim done with 0 errors.
INFO: [SIM 211-3] *************** CSIM finish ***************
INFO: [HLS 200-111] Finished Command csim_design CPU user time: 0.5 seconds. CPU system time: 0.12 seconds. Elapsed time: 0.31 seconds; current allocated memory: 189.971 MB.
INFO: [HLS 200-1510] Running: csynth_design
INFO: [HLS 200-111] Finished File checks and directory preparation: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 190.153 MB.
INFO: [HLS 200-10] Analyzing design file 'hls_example.cpp' ...
INFO: [HLS 200-111] Finished Source Code Analysis and Preprocessing: CPU user time: 13.15 seconds. CPU system time: 0.16 seconds. Elapsed time: 13.15 seconds; current allocated memory: 191.738 MB.
INFO: [HLS 200-777] Using interface defaults for 'Vivado' flow target.
WARNING: [HLS 207-586] overriding the module target triple with fpga64-xilinx-none
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
WARNING: [HLS 214-205] The INTERFACE pragma must have a max_widen_bitwidth setting that is both a power of 2 and in the range [0, 1024]. The current value of '0' will be ignored, in 'example(int*, int*)' (hls_example.cpp:27:0)
INFO: [HLS 214-115] Multiple burst reads of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'a' (hls_example.cpp:31:20)
INFO: [HLS 214-115] Multiple burst writes of length 50 and bit width 32 in loop 'VITIS_LOOP_31_1'(hls_example.cpp:31:20) has been inferred on port 'b' (hls_example.cpp:31:20)
INFO: [HLS 200-111] Finished Compiling Optimization and Transform: CPU user time: 1.99 seconds. CPU system time: 0.14 seconds. Elapsed time: 2.12 seconds; current allocated memory: 192.790 MB.
INFO: [HLS 200-111] Finished Checking Pragmas: CPU user time: 0 seconds. CPU system time: 0 seconds. Elapsed time: 0 seconds; current allocated memory: 192.792 MB.
INFO: [HLS 200-10] Starting code transformations ...
INFO: [HLS 200-111] Finished Standard Transforms: CPU user time: 0.01 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 194.585 MB.
INFO: [HLS 200-10] Checking synthesizability ...
INFO: [HLS 200-111] Finished Checking Synthesizability: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.01 seconds; current allocated memory: 194.757 MB.
INFO: [HLS 200-111] Finished Loop, function and other optimizations: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 215.907 MB.
INFO: [HLS 200-111] Finished Architecture Synthesis: CPU user time: 0.03 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 208.554 MB.
INFO: [HLS 200-10] Starting hardware synthesis ...
INFO: [HLS 200-10] Synthesizing 'example' ...
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-42] -- Implementing module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [SCHED 204-11] Starting scheduling ...
INFO: [SCHED 204-61] Pipelining loop 'VITIS_LOOP_31_1'.
INFO: [HLS 200-1470] Pipelining result : Target II = 1, Final II = 1, Depth = 4, loop 'VITIS_LOOP_31_1'
INFO: [SCHED 204-11] Finished scheduling.
INFO: [HLS 200-111] Finished Scheduling: CPU user time: 0.02 seconds. CPU system time: 0 seconds. Elapsed time: 0.03 seconds; current allocated memory: 208.848 MB.
INFO: [BIND 205-100] Starting micro-architecture generation ...
INFO: [BIND 205-101] Performing variable lifetime analysis.
INFO: [BIND 205-101] Exploring resource sharing.
INFO: [BIND 205-101] Binding ...
INFO: [BIND 205-100] Finished micro-architecture generation.
INFO: [HLS 200-111] Finished Binding: CPU user time: 0.05 seconds. CPU system time: 0 seconds. Elapsed time: 0.04 seconds; current allocated memory: 209.017 MB.
INFO: [HLS 200-10] ----------------------------------------------------------------
INFO: [HLS 200-10] -- Generating RTL for module 'example'
INFO: [HLS 200-10] ----------------------------------------------------------------
WARNING: [RTGEN 206-101] Design contains AXI ports. Reset is fixed to synchronous and active low.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/a' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on port 'example/b' to 'm_axi'.
INFO: [RTGEN 206-500] Setting interface mode on function 'example' to 'ap_ctrl_hs'.
INFO: [RTGEN 206-100] Finished creating RTL model for 'example'.
INFO: [HLS 200-111] Finished Creating RTL model: CPU user time: 0.02 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.02 seconds; current allocated memory: 209.946 MB.
INFO: [HLS 200-111] Finished Generating all RTL models: CPU user time: 0.57 seconds. CPU system time: 0.01 seconds. Elapsed time: 0.58 seconds; current allocated memory: 217.825 MB.
INFO: [VHDL 208-304] Generating VHDL RTL for example.
INFO: [VLOG 209-307] Generating Verilog RTL for example.
INFO: [HLS 200-1603] Design has MAXI bursts and missed bursts, see Vitis HLS GUI synthesis summary report for detailed information.
INFO: [HLS 200-790] **** Loop Constraint Status: All loop constraints were satisfied.
INFO: [HLS 200-789] **** Estimated Fmax: 411.00 MHz
INFO: [HLS 200-111] Finished Command csynth_design CPU user time: 15.95 seconds. CPU system time: 0.32 seconds. Elapsed time: 16.1 seconds; current allocated memory: 218.428 MB.
INFO: [HLS 200-1510] Running: cosim_design
INFO: [COSIM 212-47] Using XSIM for RTL simulation.
INFO: [COSIM 212-14] Instrumenting C test bench ...
Build using "/opt/Xilinx/Vitis_HLS/2020.2/tps/lnx64/gcc-6.2.0/bin/g++"
Compiling hls_example.cpp_pre.cpp.tb.cpp
Compiling apatb_example.cpp
Compiling apatb_example_ir.ll
Generating cosim.tv.exe
INFO: [COSIM 212-302] Starting C TB testing ...
Test passed.
INFO: [COSIM 212-333] Generating C post check test bench ...
INFO: [COSIM 212-12] Generating RTL test bench ...
INFO: [COSIM 212-1] *** C/RTL co-simulation file generation completed. ***
INFO: [COSIM 212-323] Starting verilog simulation.
INFO: [COSIM 212-15] Starting XSIM ...
Vivado Simulator 2020.2
Copyright 1986-1999, 2001-2020 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2020.2/bin/unwrapped/lnx64.o/xelab xil_defaultlib.apatb_example_top glbl -prj example.prj -L smartconnect_v1_0 -L axi_protocol_checker_v1_1_12 -L axi_protocol_checker_v1_1_13 -L axis_protocol_checker_v1_1_11 -L axis_protocol_checker_v1_1_12 -L xil_defaultlib -L unisims_ver -L xpm -L floating_point_v7_0_18 -L floating_point_v7_1_11 --lib ieee_proposed=./ieee_proposed -s example
Multi-threading is on. Using 14 slave threads.
WARNING: [XSIM 43-3431] One or more environment variables have been detected which affect the operation of the C compiler. These are typically not set in standard installations and are not tested by Xilinx, however they may be appropriate for your system, so the flow will attempt to continue. If errors occur, try running xelab with the "-mt off -v 1" switches to see more information from the C compiler. The following environment variables have been detected:
LIBRARY_PATH
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/glbl.v" into library work
INFO: [VRFC 10-311] analyzing module glbl
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_a.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_a
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/AESL_axi_master_b.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module AESL_axi_master_b
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.autotb.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module apatb_example_top
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_b_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_b_m_axi
INFO: [VRFC 10-311] analyzing module example_b_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_b_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_b_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_b_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_b_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_b_m_axi_read
INFO: [VRFC 10-311] analyzing module example_b_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example_a_m_axi.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example_a_m_axi
INFO: [VRFC 10-311] analyzing module example_a_m_axi_reg_slice
INFO: [VRFC 10-311] analyzing module example_a_m_axi_fifo
INFO: [VRFC 10-311] analyzing module example_a_m_axi_buffer
INFO: [VRFC 10-311] analyzing module example_a_m_axi_decoder
INFO: [VRFC 10-311] analyzing module example_a_m_axi_throttle
INFO: [VRFC 10-311] analyzing module example_a_m_axi_read
INFO: [VRFC 10-311] analyzing module example_a_m_axi_write
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module example
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/dump_file_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_monitor.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_fifo_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/sample_agent.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/sample_manager.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_process_interface.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/csv_file_dump.sv" into library xil_defaultlib
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/dataflow_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [nodf_module_interface.sv:4]
INFO: [VRFC 10-311] analyzing module dataflow_monitor
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'nodf_module_intf' [/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/nodf_module_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_process_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_process_intf' [df_process_interface.sv:4]
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/df_fifo_monitor.sv" into library xil_defaultlib
WARNING: [VRFC 10-3609] overwriting previous definition of interface 'df_fifo_intf' [df_fifo_interface.sv:4]
Starting static elaboration
Pass Through NonSizing Optimizer
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling package xil_defaultlib.$unit_dataflow_monitor_sv
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_a_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_a_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_a_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_a_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_a_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_a_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=96)
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=9...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DEPTH=5,DEP...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_fifo(DATA_BITS=2...
Compiling module xil_defaultlib.example_b_m_axi_write(NUM_WRITE_...
Compiling module xil_defaultlib.example_b_m_axi_buffer(DATA_WIDT...
Compiling module xil_defaultlib.example_b_m_axi_reg_slice(N=34)
Compiling module xil_defaultlib.example_b_m_axi_read(NUM_READ_OU...
Compiling module xil_defaultlib.example_b_m_axi_throttle(ADDR_WI...
Compiling module xil_defaultlib.example_b_m_axi(NUM_READ_OUTSTAN...
Compiling module xil_defaultlib.example
Compiling module xil_defaultlib.AESL_axi_master_a
Compiling module xil_defaultlib.AESL_axi_master_b
Compiling module xil_defaultlib.nodf_module_intf
Compiling module xil_defaultlib.dataflow_monitor_1
Compiling module xil_defaultlib.apatb_example_top
Compiling module work.glbl
Built simulation snapshot example
****** Webtalk v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source /home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/xsim.dir/example/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-206] Exiting Webtalk at Sun Mar 7 22:49:02 2021...
****** xsim v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source xsim.dir/example/xsim_script.tcl
# xsim {example} -autoloadwcfg -tclbatch {example.tcl}
Vivado Simulator 2020.2
Time resolution is 1 ps
source example.tcl
## run all
////////////////////////////////////////////////////////////////////////////////////
// Inter-Transaction Progress: Completed Transaction / Total Transaction
// Intra-Transaction Progress: Measured Latency / Latency Estimation * 100%
//
// RTL Simulation : "Inter-Transaction Progress" ["Intra-Transaction Progress"] @ "Simulation Time"
////////////////////////////////////////////////////////////////////////////////////
// RTL Simulation : 0 / 1 [0.00%] @ "109000"
// RTL Simulation : 1 / 1 [100.00%] @ "359000"
////////////////////////////////////////////////////////////////////////////////////
$finish called at time : 372410 ps : File "/home/hidemi/HLS/vitis_hls_examples/override_llvm_flow_demo/proj/solution1/sim/verilog/example.autotb.v" Line 462
## quit
INFO: [Common 17-206] Exiting xsim at Sun Mar 7 22:49:08 2021...
INFO: [COSIM 212-316] Starting C post checking ...
Test passed.
INFO: [COSIM 212-1000] *** C/RTL co-simulation finished: PASS ***
INFO: [COSIM 212-211] II is measurable only when transaction number is greater than 1 in RTL simulation. Otherwise, they will be marked as all NA. If user wants to calculate them, please make sure there are at least 2 transactions in RTL simulation.
INFO: [HLS 200-111] Finished Command cosim_design CPU user time: 17.19 seconds. CPU system time: 0.73 seconds. Elapsed time: 17.29 seconds; current allocated memory: 222.565 MB.
INFO: [HLS 200-1510] Running: export_design -rtl verilog
INFO: [IMPL 213-8] Exporting RTL as a Vivado IP.
****** Vivado v2020.2 (64-bit)
**** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
**** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
source run_ippack.tcl -notrace
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [Common 17-206] Exiting Vivado at Sun Mar 7 22:49:16 2021...
INFO: [HLS 200-802] Generated output file proj/solution1/impl/export.zip
INFO: [HLS 200-111] Finished Command export_design CPU user time: 8.76 seconds. CPU system time: 0.59 seconds. Elapsed time: 10.9 seconds; current allocated memory: 227.530 MB.
INFO: [HLS 200-112] Total CPU user time: 43.79 seconds. Total CPU system time: 2.02 seconds. Total elapsed time: 45.62 seconds; peak allocated memory: 217.825 MB.
INFO: [Common 17-206] Exiting vitis_hls at Sun Mar 7 22:49:19 2021...HLSの結果は次のようにVerilogHDLとかがで生成されました。
$ ls proj/solution1/syn/verilog/
example.v example_a_m_axi.v example_b_m_axi.v
VitisAIは次のURLからダウンロードできる。
https://github.com/Xilinx/Vitis-AI.git
本日の時点でバージョンは周辺のアプリケーションも含めて次のとおりである。
VitisAIの最新バージョンを使用するならgithubのmasterかv1.3のブランチを使うのが良いだろう。
User GuideはUG1414でバージョンはv1.3、URLはつぎのところである。
https://www.xilinx.com/support/documentation/sw_manuals/vitis_ai/1_3/ug1414-vitis-ai.pdf
Webでもドキュメントを見ることがき、つぎのURLである。
https://www.xilinx.com/html_docs/vitis_ai/1_3/
Getting StartをするならgithubのREADME.txtを見るのが一番い良い。
現時点ではWebで検索するとv1.2のドキュメントによく遭遇するので注意しておくとよいだろう。
基本的にVitisAIはdocker環境で提供されている。
docker次隊のインストール方法もドキュメントに記載されているのでさそれを参照してインストールを進めれば良い。
そして、docker環境はつぎの2つがある。
環境に合わせて使用すれば良い。
ただし、GPU環境ではnVIDIAのdocker環境も必要になる。
Exampleとしてつぎの4つの大項目がある。
VARTはVitis AI Runtimeの略である。
VARTはつぎのRunTime APIを使用できる。
XRT（Xilinx Runtime Library）とは違うものなので注意が必要である。
Vitis AI LibraryはDPU（Deep-Learning Processor Unit）を使用した推論用に構築されたライブラリとAPIのセットである。
各フレームワークでサポートしているライブラリはつぎのとおりである。
DNNDKはDeep Neural Network Development Kitの略である。
VGG、ResNet、GoogleNet、YOLO、SSD、MobileNet、FPNなどのCNNをサポートしている。
DNNDKはDPUCZDX8Gを実行するための環境が提供されてる。
なぁ〜んとなく、Vitis AIの構造というかgithubの中身の構成が分かってきた。
Quantizer（量子化）がライブラリだと思っていたのでVitis AI Libraryに属しているんだろうと思い込んでVitis AIの構造を理解しようとしてたから訳がわからなくなってしまってた。
toolsのディレクトリを確認するとつぎのようになっており、Quantizerはライブラリとは分けられていることがわかる。
$ ls tools/
AKS RNN Vitis-AI-Library Vitis-AI-Profiler Vitis-AI-Quantizer Vitis-AI-Runtimeつまり、Vitis AIで構造を紹介している下図のとおり、QuantizerとLibraryは違うものと思えば良かったんだ。
ざっと、自分の中で整理できたところで、自分自身が欲しいものを考えるとこの図からはCompiler、Quantizer、Optimizer、Profilerとなる。
つまり、Vitis AI LibraryとDNNDKは必要ないということで良いだろう。
write: 2021/01/28/ 23:30:00
Xilinxの公式ドキュメントには次のように記載されている。
「vai_q_pytorch には現在 GPU バージョンだけがあり、vitis-ai-pytorch 環境は GPU コンテナー内にのみ存在します。」
どういう意味？
無いってこと？
今度はちゃんとREADME.txtを読みながら進めるぞ！
README.txtによると次のようにインストールする。
export CUDA_HOME=/usr/local/cuda
pip3 install torch==1.4.0 torchvision==0.5.0
pip3 install -r requirements.txt
cd ./pytorch_binding
python3 setup.py install
python3 setup.py developそして、次のコマンドを実行する。
python3 -c "import pytorch_nndct"あれ、どこかで見かけたな…
$ python3 -c "import pytorch_nndct"
Traceback (most recent call last):
File "<string>", line 1, in <module>
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/__init__.py", line 12, in <module>
from .apis import *
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/apis.py", line 24, in <module>
from .qproc import TorchQuantProcessor
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/qproc/__init__.py", line 1, in <module>
from .base import TorchQuantProcessor, dump_xmodel
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/qproc/base.py", line 30, in <module>
from pytorch_nndct.quantization import TORCHQuantizer
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/quantization/__init__.py", line 2, in <module>
from .quant_aware_training import QatScheduler
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/quantization/quant_aware_training.py", line 28, in <module>
from pytorch_nndct.nn.qat.modules import conv_fused
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/nn/__init__.py", line 1, in <module>
from .modules import *
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/nn/modules/__init__.py", line 2, in <module>
from .linear import *
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/nn/modules/linear.py", line 26, in <module>
from .fix_ops import NndctScale
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/nn/modules/fix_ops.py", line 22, in <module>
from ..load_kernels import nndct_kernels
File "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Quantizer/vai_q_pytorch/pytorch_binding/pytorch_nndct/nn/load_kernels.py", line 87, in <module>
nndct_kernels = load(
File "/usr/local/lib/python3.8/dist-packages/torch/utils/cpp_extension.py", line 670, in load
return _jit_compile(
File "/usr/local/lib/python3.8/dist-packages/torch/utils/cpp_extension.py", line 857, in _jit_compile
_write_ninja_file_and_build(
File "/usr/local/lib/python3.8/dist-packages/torch/utils/cpp_extension.py", line 907, in _write_ninja_file_and_build
_write_ninja_file(
File "/usr/local/lib/python3.8/dist-packages/torch/utils/cpp_extension.py", line 1150, in _write_ninja_file
cuda_flags = common_cflags + COMMON_NVCC_FLAGS + _get_cuda_arch_flags()
File "/usr/local/lib/python3.8/dist-packages/torch/utils/cpp_extension.py", line 1027, in _get_cuda_arch_flags
raise ValueError("Unknown CUDA arch ({}) or GPU not supported".format(arch))
ValueError: Unknown CUDA arch (8.6) or GPU not supportedなんでエラーなの？
そういえば、昨日までこのコマンドを使ってたよなぁ。
あ、たぶん、バージョンをデグレしちゃったなぁ。
バージョンを確認しよう。
$ pip3 list |grep torch
pytorch-ignite 0.4.2
pytorch-nndct 0.1.0+eeafe77 /usr/local/lib/python3.8/dist-packages
torch 1.4.0 /usr/local/lib/python3.8/dist-packages
torchvision 0.5.0やっぱり、ダメやん。
もう一度、インストールする。
$ pip3 list |grep torch
pytorch-ignite 0.4.2
pytorch-nndct 0.1.0+eeafe77 /usr/local/lib/python3.8/dist-packages
torch 1.8.0a0+unknown /usr/local/lib/python3.8/dist-packages
torchvision 0.9.0a0+d732562確認してみよう。
$ python3 -c "import pytorch_nndct"
[NNDCT_NOTE]: Loading NNDCT kernels...OKだな。
それでここからどうすんの？
試すのは次を使えばいいみたい。
./tools/Vitis-AI-Quantizer/vai_q_pytorch/example/resnet18_quant.py
$ cd Vitis-AI-Quantizer/vai_q_pytorch/example/
$ ls
mobilenetv2_fast_finetune.py resnet18_quant.py resnet18_quantize_finetuning.pyソースコードは次ので良いみたい。
resnet18_quant.py
$ python3 resnet18_quant.py --quant_mode calib --subset_len 200
[NNDCT_NOTE]: Loading NNDCT kernels...
-------- Start resnet18 test
Traceback (most recent call last):
File "resnet18_quant.py", line 280, in <module>
quantization(
File "resnet18_quant.py", line 203, in quantization
model.load_state_dict(torch.load(file_path))
File "/usr/local/lib/python3.8/dist-packages/torch/serialization.py", line 579, in load
with _open_file_like(f, 'rb') as opened_file:
File "/usr/local/lib/python3.8/dist-packages/torch/serialization.py", line 230, in _open_file_like
return _open_file(name_or_buffer, mode)
File "/usr/local/lib/python3.8/dist-packages/torch/serialization.py", line 211, in __init__
super(_open_file, self).__init__(open(name, mode))
FileNotFoundError: [Errno 2] No such file or directory: '/path/to/trained_model/resnet18.pth'エラーになったんだですがなにか忘れてます？
resnet18.pthのPathを合わせないといけないようですね。
$ wget https://download.pytorch.org/models/resnet18-5c106cde.pth
$ mv resnet18-5c106cde.pth resnet18.pth$ python3 resnet18_quant.py --quant_mode calib --subset_len 200 --model_dir=./
[NNDCT_NOTE]: Loading NNDCT kernels...
-------- Start resnet18 test
[NNDCT_NOTE]: Quantization calibration process start up...
[NNDCT_NOTE]: =>Quant Module is in 'cuda'.
[NNDCT_NOTE]: =>Parsing ResNet...
Traceback (most recent call last):
File "resnet18_quant.py", line 280, in <module>
quantization(
File "resnet18_quant.py", line 211, in quantization
quantizer = torch_quantizer(
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/apis.py", line 63, in __init__
self.processor = TorchQuantProcessor(quant_mode = quant_mode,
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/qproc/base.py", line 113, in __init__
quant_module, graph = prepare_quantizable_module(
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/qproc/utils.py", line 160, in prepare_quantizable_module
graph = parse_module(module, input_args)
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/qproc/utils.py", line 73, in parse_module
graph = parser(module._get_name() if graph_name is None else graph_name,
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/parse/parser.py", line 32, in __call__
raw_graph = torch_graph_handler.build_torch_graph(graph_name, module, input_args)
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/parse/trace_helper.py", line 37, in build_torch_graph
fw_graph, params = self._trace_graph_from_model(input_args, train)
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/parse/trace_helper.py", line 58, in _trace_graph_from_model
graph, output = trace_and_get_graph_from_model(self._module, input_args,
File "/usr/local/lib/python3.8/dist-packages/pytorch_nndct/parse/utils.py", line 183, in trace_and_get_graph_from_model
old_map = torch.jit._trace_module_map
AttributeError: module 'torch.jit' has no attribute '_trace_module_map'pyhtorchのソースコードを読むと_trace_module_mapは次のように書いているが関係あるかな？
# By default, training=False, which is good because running a model in
# training mode could result in internal buffers getting updated, dropout
# getting applied, etc. If you really know what you're doing, you
# can turn training=True (or None, to preserve whatever the original
# training mode was.)あ、それよりもtorch.jitでget_trace_graphがなかったら、_trace_module_mapを選択してしまうようだな。
キーワードはget_trace_graphっぽいんだけど、
pytorchの中に入り始めたのでこれ以上、深追いするのはやめよう。
write: 2021/01/27/ 22:16:48
vartのビルドにはlibjson-cってのがいるらしい。
sudo apt install libjson-c-devそして、ビルドする。
./cmake.sh --build-python --pack debxirのときにpythonのlinkを変えたから、もう、もんだいないでしょう…
おぉ〜、openCVがいるのね。
Webページを見たら4.5.1が最新だったのでビルドしてインストールする。
unzip opencv-4.5.1.zip
cd opencv-4.5.1
mkdir build
cd build
cmake ../
makeなんかだんだんとVitisAIのインストールから離れていっている。
いつ、戻ってこれるのか？
ビルドが完了したところで、正解の手順をまとめよう。
write: 2021/01/26/ 23:56:23
ビルドしたxirを検証したらこんな感じでパッケージを読んでくれない。
$ python3 -c "import pytorch_nndct"
[NNDCT_WARN]: Can't find xir package in your environment.
[NNDCT_NOTE]: Loading NNDCT kernels...これダメなんだろうなぁ…
どこかでxirをpython2.7に入れる設定が紛れ込んでしまうのが原因だろう。
と、いうか、これいうのがあるからpythonって嫌いなんだよな。
xirのソースディレクトリでpythonを調べると次のように教示される。
$ grep -R -i python
cmake.sh: -l help,clean,conda,build-only,build-python,user,home,type:,pack:,build-dir:,install-prefix:,cmake-options: \
cmake.sh: --build-python) build_python=true;;
cmake.sh:# build python
cmake.sh:if ${build_python:=false}; then
cmake.sh: args+=(-DBUILD_PYTHON=ON)
cmake.sh: args+=(-DBUILD_PYTHON=OFF)
cmake.sh: echo " --build-python build python. if --pack is declared, will build conda package"
README.md:XIR also provides Python APIs which named PyXIR. It enables Python users to fully access the XIR and get benefits in the pure Python environment, e.g. co-develop and integrate users' Python project with the current XIR based tools without massive dirty work to fix the gap between two languages.
README.md:./cmake.sh --build-python --user
.gitlab-ci.yml: - ./cmake.sh --clean --build-python
.gitlab-ci.yml: - ./cmake.sh --clean --build-python
src/python/wrapper/wrapper.cpp:// python 3.7 deprecate PyCreateThread, but pybind11 2.2.3 still uses
src/python/wrapper/wrapper.cpp: m.doc() = "pyxir module for python bindings";
src/python/CMakeLists.txt:set(PYTHON_BUILD_PATH ${CMAKE_BINARY_DIR}/python)
src/python/CMakeLists.txt: find_path(_PYBIND11_PATH pybind11 HINTS /usr/include/python3.7m)
src/python/CMakeLists.txt: message(WARNING "PYBIND11 NOT FOUND. python extenions for vitis dpu runner will not be built.")
src/python/CMakeLists.txt: find_package(Python3 REQUIRED COMPONENTS Development)
src/python/CMakeLists.txt:include/python${Python3_VERSION_MAJOR}.${Python3_VERSION_MINOR}m;${CMAKE_SOURCE_DIR}/include;${CMAKE_SOURCE_DIR}/src"
src/python/CMakeLists.txt: -lpython${Python3_VERSION_MAJOR}.${Python3_VERSION_MINOR}m
src/python/CMakeLists.txt: set(PYTHON_SITE_PACKAGES_USER "lib/python${Python3_VERSION_MAJOR}.${Python3_VERSION_MINOR}/site-packages")
src/python/CMakeLists.txt: set(PYTHON_SITE_PACKAGES "lib/python${Python3_VERSION_MAJOR}.${Python3_VERSION_MINOR}/site-packages")
src/python/CMakeLists.txt: execute_process(COMMAND "${PYTHON_EXECUTABLE}" "-m" "site" "--user-site"
src/python/CMakeLists.txt: OUTPUT_VARIABLE PYTHON_SITE_PACKAGES_USER)
src/python/CMakeLists.txt: string(REGEX REPLACE "\n" "" PYTHON_SITE_PACKAGES_USER ${PYTHON_SITE_PACKAGES_USER})
src/python/CMakeLists.txt: install(TARGETS ${TARGET_NAME} DESTINATION lib/python)
src/python/CMakeLists.txt: install(TARGETS ${TARGET_NAME} DESTINATION ${PYTHON_SITE_PACKAGES_USER})
src/python/CMakeLists.txt: install(TARGETS ${TARGET_NAME} DESTINATION ${PYTHON_SITE_PACKAGES})
src/xir/op/shape_inference.cpp: // https://www.tensorflow.org/api_docs/python/tf/keras/layers/Flatten,
src/CMakeLists.txt:if(BUILD_PYTHON)
src/CMakeLists.txt: add_subdirectory(python)
CMakeLists.txt:option(BUILD_PYTHON "build python interface" OFF)
CMakeLists.txt:option(INSTALL_HOME "install python lib in cmake install path" OFF)
CMakeLists.txt:option(INSTALL_USER "install python lib in user space" OFF)これからすると次のファイルのどこかだと思われる。
順当に行けば、cmake.sh、.gitlab-ci.yml、CMakeLists.txtは除外されるだろう。
それとPython3_も省いてよいだろう。
残る部分は下記のところかな？
$ grep -R -i python
src/python/CMakeLists.txt: execute_process(COMMAND "${PYTHON_EXECUTABLE}" "-m" "site" "--user-site"
src/python/CMakeLists.txt: OUTPUT_VARIABLE PYTHON_SITE_PACKAGES_USER)
src/python/CMakeLists.txt: string(REGEX REPLACE "\n" "" PYTHON_SITE_PACKAGES_USER ${PYTHON_SITE_PACKAGES_USER})
src/python/CMakeLists.txt: install(TARGETS ${TARGET_NAME} DESTINATION lib/python)
src/python/CMakeLists.txt: install(TARGETS ${TARGET_NAME} DESTINATION ${PYTHON_SITE_PACKAGES_USER})
src/python/CMakeLists.txt: install(TARGETS ${TARGET_NAME} DESTINATION ${PYTHON_SITE_PACKAGES})
src/CMakeLists.txt: add_subdirectory(python)そうなると一番怪しいのはPYTHON_EXECUTABLEなんだな。
messageをだしてみると、/usr/bin/pythonに向いていた。
src/python/CMakeLists.txtの次のところでPYTHON_SITE_PACKAGES_USERが/home/hidemi/.local/lib/python2.7/site-packagesに向いていた。
execute_process(COMMAND "${PYTHON_EXECUTABLE}" "-m" "site" "--user-site"
OUTPUT_VARIABLE PYTHON_SITE_PACKAGES_USER)じゃぁ、PYTHON_EXECUTABLEって、どこから設定されるの？
それがわからないのでちょっと強引だけど次のように修正した。
execute_process(COMMAND "${PYTHON_EXECUTABLE}3" "-m" "site" "--user-site"
OUTPUT_VARIABLE PYTHON_SITE_PACKAGES_USER)そしてビルドして…
$ ./cmake.sh --build-python --user
Native-platform building...
No LSB modules are available.
No LSB modules are available.
cd /home/hidemi/build/build.Ubuntu.20.04.x86_64.Debug/xir
cmake -DBUILD_TEST=ON -DBUILD_CONTRIB=OFF -DBUILD_DOC=OFF -DCMAKE_BUILD_TYPE=Debug -DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DBUILD_PYTHON=ON -DINSTALL_HOME=OFF -DINSTALL_USER=ON -DCMAKE_INSTALL_PREFIX=/home/hidemi/.local/Ubuntu.20.04.x86_64.Debug /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Runtime/VART/xir
-- Found importable target unilog::unilog: /usr/local/lib/libunilog.so.1.3.0
PYTHON_BUILD_PATH is /home/hidemi/build/build.Ubuntu.20.04.x86_64.Debug/xir/python
PYTHON_EXECUTABLE is /usr/bin/python
PYTHON_SITE_PACKAGES_USER is /home/hidemi/.local/lib/python3.8/site-packages
-- Configuring done
-- Generating done
-- Build files have been written to: /home/hidemi/build/build.Ubuntu.20.04.x86_64.Debug/xir
Scanning dependencies of target xir
[ 1%] Building C object src/xir/CMakeFiles/xir.dir/version.c.o
[ 3%] Linking CXX shared library libxir.so
[ 45%] Built target xir
[ 46%] Linking CXX executable test_c_api
[ 48%] Linking CXX shared module xir.so
[ 50%] Linking CXX executable test_deserialize_model.bin
[ 53%] Linking CXX executable test_graph_impl.bin
[ 53%] Linking CXX executable test_graph_iso.bin
[ 54%] Linking CXX executable test_graph_template.bin
[ 56%] Linking CXX executable test_c_api.bin
[ 58%] Linking CXX executable test_deserialize.bin
[ 59%] Linking CXX executable demo.bin
[ 61%] Linking CXX executable test_subgraph_iso.bin
[ 62%] Linking CXX executable test_subgraph_topo.bin
[ 64%] Linking CXX executable xir
[ 66%] Linking CXX executable test_subgraph.bin
[ 67%] Built target test_subgraph_iso.bin
[ 69%] Built target test_subgraph.bin
[ 70%] Built target test_c_api
[ 72%] Built target demo.bin
[ 74%] Built target test_c_api.bin
[ 75%] Built target test_graph_template.bin
[ 77%] Built target test_deserialize_model.bin
[ 79%] Built target test_graph_iso.bin
[ 80%] Built target test_graph_impl.bin
[ 82%] Built target test_deserialize.bin
[ 83%] Built target test_subgraph_topo.bin
[ 96%] Built target xir_util
[100%] Built target wrapper
[ 45%] Built target xir
[ 50%] Built target wrapper
[ 64%] Built target xir_util
[ 67%] Built target test_c_api
[ 70%] Built target test_deserialize_model.bin
[ 74%] Built target test_graph_impl.bin
[ 77%] Built target test_graph_iso.bin
[ 80%] Built target test_graph_template.bin
[ 83%] Built target test_subgraph_iso.bin
[ 87%] Built target demo.bin
[ 90%] Built target test_c_api.bin
[ 93%] Built target test_deserialize.bin
[ 96%] Built target test_subgraph.bin
[100%] Built target test_subgraph_topo.bin
Install the project...
-- Install configuration: "Debug"
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-config.cmake
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-config-version.cmake
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so.1.3.0
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so.1
-- Set runtime path of "/home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so.1.3.0" to "/usr/local/lib"
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/xir.h
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/op/op.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/op/op_def.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/attrs/attrs.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/attrs/attr_def.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/attrs/attr_expander.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/util/any.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/util/tool_function.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/util/data_type.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/graph/graph.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/graph/graph_template.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/graph/subgraph.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/tensor/tensor.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-targets.cmake
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-targets-debug.cmake
-- Installing: /home/hidemi/.local/lib/python3.8/site-packages/xir.so
-- Set runtime path of "/home/hidemi/.local/lib/python3.8/site-packages/xir.so" to "/usr/local/lib"
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/bin/xir
-- Set runtime path of "/home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/bin/xir" to "/usr/local/lib"なんとか、/home/hidemi/.local/lib/python3.8/site-packages/xir.soにインストールされた。
でも、これでうまく行くとは限らない。
$ python3 -c "import pytorch_nndct"
[NNDCT_WARN]: Can't find xir package in your environment.
[NNDCT_NOTE]: Loading NNDCT kernels...やっぱり…
念のため、packageを確認するといるんだけどなぁ。
$ pip3 list
xir 0.0.3nndctも確認するか…
pytorch-nndct 0.1.0+eeafe77 /usr/local/lib/python3.8/dist-packagesnndctはLocationがでているけど、xirは出ていない。
ここの差か？
ちょっと頑張って調べたら、pytorch-nndctの次のところでエラーしてるようだ。
from xir import Graphもしかして、これ？
$ python3 -c "import xir"
Traceback (most recent call last):
File "<string>", line 1, in <module>
ImportError: /home/hidemi/.local/lib/python3.8/site-packages/xir.so: undefined symbol: _Py_ZeroStruct_Py_ZeroStructってなんなのぉ〜！！！
どうも、バージョン違いでビルドしちゃってるみたいなのだ。
あ、xirのビルドログをよく見ると2.7を見ているっぽい。
-- Found PythonInterp: /usr/bin/python (found version "2.7.18")
-- Found PythonLibs: /usr/lib/x86_64-linux-gnu/libpython2.7.soもう、嫌になってきたのでpython2.7のlinkを変更した。
$ sudo rm /usr/bin/python
$ ln -s /usr/bin/python3 /usr/bin/pythonこれでpython3.8に振り向いただろう。
$ ./cmake.sh --build-python --user --pack deb
Native-platform building...
No LSB modules are available.
No LSB modules are available.
cd /home/hidemi/build/build.Ubuntu.20.04.x86_64.Debug/xir
cmake -DBUILD_TEST=ON -DBUILD_CONTRIB=OFF -DBUILD_DOC=OFF -DCPACK_GENERATOR=DEB -DCMAKE_BUILD_TYPE=Debug -DCMAKE_EXPORT_COMPILE_COMMANDS=ON -DBUILD_PYTHON=ON -DINSTALL_HOME=OFF -DINSTALL_USER=ON -DCMAKE_INSTALL_PREFIX=/home/hidemi/.local/Ubuntu.20.04.x86_64.Debug /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Runtime/VART/xir
-- The C compiler identification is GNU 9.3.0
-- The CXX compiler identification is GNU 9.3.0
-- Detecting C compiler ABI info
-- Detecting C compiler ABI info - done
-- Check for working C compiler: /usr/bin/cc - skipped
-- Detecting C compile features
-- Detecting C compile features - done
-- Detecting CXX compiler ABI info
-- Detecting CXX compiler ABI info - done
-- Check for working CXX compiler: /usr/bin/c++ - skipped
-- Detecting CXX compile features
-- Detecting CXX compile features - done
-- Found importable target unilog::unilog: /usr/local/lib/libunilog.so.1.3.0
-- Found OpenSSL: /usr/lib/x86_64-linux-gnu/libcrypto.so (found version "1.1.1f")
-- Found Boost: /usr/lib/x86_64-linux-gnu/cmake/Boost-1.71.0/BoostConfig.cmake (found version "1.71.0")
-- Found Protobuf: /usr/lib/x86_64-linux-gnu/libprotobuf.so;-lpthread (found version "3.6.1")
PYTHON_BUILD_PATH is /home/hidemi/build/build.Ubuntu.20.04.x86_64.Debug/xir/python
-- Found PythonInterp: /usr/bin/python (found version "3.8.5")
-- Found PythonLibs: /usr/lib/x86_64-linux-gnu/libpython3.8.so
-- Performing Test HAS_FLTO
-- Performing Test HAS_FLTO - Success
-- LTO enabled
PYTHON_EXECUTABLE is /usr/bin/python
PYTHON_SITE_PACKAGES_USER is /home/hidemi/.local/lib/python3.8/site-packages
-- Configuring done
-- Generating done
-- Build files have been written to: /home/hidemi/build/build.Ubuntu.20.04.x86_64.Debug/xir
[ 1%] Running cpp protocol buffer compiler on /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Runtime/VART/xir/src/xir/proto/graph_proto_v2.proto
[ 3%] Running cpp protocol buffer compiler on /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/tools/Vitis-AI-Runtime/VART/xir/src/xir/proto/graph_proto_v1.proto
Scanning dependencies of target xir
[ 4%] Building CXX object src/xir/CMakeFiles/xir.dir/graph_proto_v1.pb.cc.o
[ 6%] Building CXX object src/xir/CMakeFiles/xir.dir/graph_proto_v2.pb.cc.o
[ 8%] Building CXX object src/xir/CMakeFiles/xir.dir/util/data_type.cpp.o
[ 9%] Building CXX object src/xir/CMakeFiles/xir.dir/util/error_code.cpp.o
[ 11%] Building CXX object src/xir/CMakeFiles/xir.dir/util/internal_util.cpp.o
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[ 17%] Building CXX object src/xir/CMakeFiles/xir.dir/attrs/attrs.cpp.o
[ 19%] Building CXX object src/xir/CMakeFiles/xir.dir/attrs/attrs_imp.cpp.o
[ 20%] Building CXX object src/xir/CMakeFiles/xir.dir/op/built_in_ops.cpp.o
[ 22%] Building CXX object src/xir/CMakeFiles/xir.dir/op/op_def.cpp.o
[ 24%] Building CXX object src/xir/CMakeFiles/xir.dir/op/op_def_factory_imp.cpp.o
[ 25%] Building CXX object src/xir/CMakeFiles/xir.dir/op/op_imp.cpp.o
[ 27%] Building CXX object src/xir/CMakeFiles/xir.dir/op/shape_inference.cpp.o
[ 29%] Building CXX object src/xir/CMakeFiles/xir.dir/graph/elf2xir.cpp.o
[ 30%] Building CXX object src/xir/CMakeFiles/xir.dir/graph/graph.cpp.o
[ 32%] Building CXX object src/xir/CMakeFiles/xir.dir/graph/graph_imp.cpp.o
[ 33%] Building CXX object src/xir/CMakeFiles/xir.dir/graph/graph_template.cpp.o
[ 35%] Building CXX object src/xir/CMakeFiles/xir.dir/graph/graph_template_imp.cpp.o
[ 37%] Building CXX object src/xir/CMakeFiles/xir.dir/graph/serialize_v2.cpp.o
[ 38%] Building CXX object src/xir/CMakeFiles/xir.dir/graph/subgraph_imp.cpp.o
[ 40%] Building CXX object src/xir/CMakeFiles/xir.dir/tensor/tensor.cpp.o
[ 41%] Building CXX object src/xir/CMakeFiles/xir.dir/tensor/tensor_imp.cpp.o
[ 43%] Building C object src/xir/CMakeFiles/xir.dir/version.c.o
[ 45%] Linking CXX shared library libxir.so
[ 45%] Built target xir
Scanning dependencies of target wrapper
Scanning dependencies of target test_c_api
Scanning dependencies of target xir_util
Scanning dependencies of target test_deserialize_model.bin
Scanning dependencies of target test_graph_impl.bin
Scanning dependencies of target test_graph_template.bin
Scanning dependencies of target test_graph_iso.bin
Scanning dependencies of target test_subgraph_iso.bin
Scanning dependencies of target test_subgraph.bin
Scanning dependencies of target demo.bin
Scanning dependencies of target test_c_api.bin
Scanning dependencies of target test_deserialize.bin
Scanning dependencies of target test_subgraph_topo.bin
[ 46%] Building C object test/CMakeFiles/test_c_api.dir/test_c_api.c.o
[ 48%] Building CXX object test/CMakeFiles/test_deserialize_model.bin.dir/test_deserialize_model.cpp.o
[ 50%] Building CXX object test/CMakeFiles/test_graph_template.bin.dir/test_graph_template.cpp.o
[ 51%] Building CXX object test/CMakeFiles/test_graph_impl.bin.dir/test_graph_impl.cpp.o
[ 53%] Building CXX object test/CMakeFiles/test_graph_iso.bin.dir/test_graph_iso.cpp.o
[ 56%] Building CXX object src/python/CMakeFiles/wrapper.dir/wrapper/wrapper.cpp.o
[ 56%] Building CXX object test/CMakeFiles/test_subgraph_iso.bin.dir/test_subgraph_iso.cpp.o
[ 59%] Building C object test/CMakeFiles/test_c_api.bin.dir/test_c_api.c.o
[ 59%] Building CXX object test/CMakeFiles/test_deserialize.bin.dir/test_deserialize.cpp.o
[ 61%] Building CXX object src/python/CMakeFiles/wrapper.dir/wrapper/pyxir_error_code.cpp.o
[ 62%] Building CXX object test/CMakeFiles/test_subgraph.bin.dir/test_subgraph.cpp.o
[ 64%] Building CXX object test/CMakeFiles/demo.bin.dir/demo.cpp.o
[ 66%] Building CXX object test/CMakeFiles/test_subgraph_topo.bin.dir/test_subgraph_topo.cpp.o
[ 67%] Building CXX object tools/CMakeFiles/xir_util.dir/xir_util.cpp.o
[ 70%] Building CXX object tools/CMakeFiles/xir_util.dir/cmd_png.cpp.o
[ 70%] Building CXX object tools/CMakeFiles/xir_util.dir/cmd_dump_reg.cpp.o
[ 72%] Building CXX object tools/CMakeFiles/xir_util.dir/cmd_svg.cpp.o
[ 74%] Building CXX object tools/CMakeFiles/xir_util.dir/cmd_dump_txt.cpp.o
[ 75%] Building CXX object tools/CMakeFiles/xir_util.dir/cmd_subgraph.cpp.o
[ 77%] Building CXX object tools/CMakeFiles/xir_util.dir/cmd_dump_code.cpp.o
[ 79%] Building CXX object tools/CMakeFiles/xir_util.dir/cmd_graph.cpp.o
[ 80%] Linking CXX executable test_c_api
[ 82%] Linking CXX executable test_c_api.bin
[ 82%] Built target test_c_api
[ 82%] Built target test_c_api.bin
[ 83%] Linking CXX executable test_deserialize.bin
[ 85%] Linking CXX executable test_deserialize_model.bin
[ 87%] Linking CXX executable test_graph_template.bin
[ 88%] Linking CXX executable test_graph_impl.bin
[ 88%] Built target test_deserialize.bin
[ 88%] Built target test_deserialize_model.bin
[ 88%] Built target test_graph_template.bin
[ 90%] Linking CXX executable test_subgraph_iso.bin
[ 91%] Linking CXX executable test_subgraph.bin
[ 91%] Built target test_graph_impl.bin
[ 93%] Linking CXX executable test_subgraph_topo.bin
[ 95%] Linking CXX executable demo.bin
[ 96%] Linking CXX executable test_graph_iso.bin
[ 96%] Built target test_subgraph.bin
[ 96%] Built target test_subgraph_iso.bin
[ 96%] Built target test_subgraph_topo.bin
[ 96%] Built target demo.bin
[ 96%] Built target test_graph_iso.bin
[ 98%] Linking CXX executable xir
[ 98%] Built target xir_util
[100%] Linking CXX shared module xir.cpython-38-x86_64-linux-gnu.so
[100%] Built target wrapper
[ 45%] Built target xir
[ 50%] Built target wrapper
[ 64%] Built target xir_util
[ 67%] Built target test_c_api
[ 70%] Built target test_deserialize_model.bin
[ 74%] Built target test_graph_impl.bin
[ 77%] Built target test_graph_iso.bin
[ 80%] Built target test_graph_template.bin
[ 83%] Built target test_subgraph_iso.bin
[ 87%] Built target demo.bin
[ 90%] Built target test_c_api.bin
[ 93%] Built target test_deserialize.bin
[ 96%] Built target test_subgraph.bin
[100%] Built target test_subgraph_topo.bin
Install the project...
-- Install configuration: "Debug"
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-config.cmake
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-config-version.cmake
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so.1.3.0
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so.1
-- Set runtime path of "/home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so.1.3.0" to "/usr/local/lib"
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/lib/libxir.so
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/xir.h
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/op/op.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/op/op_def.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/attrs/attrs.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/attrs/attr_def.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/attrs/attr_expander.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/util/any.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/util/tool_function.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/util/data_type.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/graph/graph.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/graph/graph_template.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/graph/subgraph.hpp
-- Up-to-date: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/include/xir/tensor/tensor.hpp
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-targets.cmake
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/share/cmake/xir/xir-targets-debug.cmake
-- Installing: /home/hidemi/.local/lib/python3.8/site-packages/xir.cpython-38-x86_64-linux-gnu.so
-- Set runtime path of "/home/hidemi/.local/lib/python3.8/site-packages/xir.cpython-38-x86_64-linux-gnu.so" to "/usr/local/lib"
-- Installing: /home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/bin/xir
-- Set runtime path of "/home/hidemi/.local/Ubuntu.20.04.x86_64.Debug/bin/xir" to "/usr/local/lib"
[ 45%] Built target xir
[ 50%] Built target wrapper
[ 64%] Built target xir_util
[ 67%] Built target test_c_api
[ 70%] Built target test_deserialize_model.bin
[ 74%] Built target test_graph_impl.bin
[ 77%] Built target test_graph_iso.bin
[ 80%] Built target test_graph_template.bin
[ 83%] Built target test_subgraph_iso.bin
[ 87%] Built target demo.bin
[ 90%] Built target test_c_api.bin
[ 93%] Built target test_deserialize.bin
[ 96%] Built target test_subgraph.bin
[100%] Built target test_subgraph_topo.bin
Run CPack packaging tool...
CPack: Create package using DEB
CPack: Install projects
CPack: - Run preinstall target for: xir
CPack: - Install project: xir []
CPack: Create package
CPack: - package: /home/hidemi/build/build.Ubuntu.20.04.x86_64.Debug/xir/libxir_1.3.0_amd64.deb generated.よし、ひとまずOKだ。
$ python3 -c "import pytorch_nndct"
[NNDCT_NOTE]: Loading NNDCT kernels...