ハードウェアは近くまでたどり着いていると思うのでそこを中心に探してみます。
昨日のtclファイルがプロジェクトの大元なんだろう。
そうだとすると、./Vitis-AI/dsa/DPU-TRD/prjあたりでfindするとわかるよね。
$ find ./Vitis-AI/dsa/DPU-TRD/prj
./Vitis-AI/dsa/DPU-TRD/prj
./Vitis-AI/dsa/DPU-TRD/prj/Vitis
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/Makefile
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/zcu102_lowpower.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/zcu104_lowpower.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts/gen_dpu_xo.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts/package_sfm_kernel.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts/package_dpu_kernel.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts/gen_sfm_xo.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_102_3dpu
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_1dpu
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_102_3dpu_LPD
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_gui
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/kernel_xml
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/kernel_xml/dpu
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/kernel_xml/dpu/kernel.xml
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/kernel_xml/sfm
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/kernel_xml/sfm/kernel.xml
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/README.md
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.5.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/ide.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/5.3.3.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.6.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.4.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.13.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.9.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/app.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/URL.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.12.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.8.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/dpu_hardware_arch.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.10.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/sysroot.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.11.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.2.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.1.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.7.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.15.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/install.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/download.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/prj_conf.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/6.14.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/doc/softmax.png
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts_gui
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts_gui/gen_dpu_xo.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts_gui/package_sfm_kernel.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts_gui/package_dpu_kernel.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vitis/scripts_gui/gen_sfm_xo.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vivado
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/scripts
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/scripts/base
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/scripts/base/trd_bd.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/scripts/trd_prj.tcl
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/constrs
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/constrs/timing.xdc
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/constrs/debug.xdc
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/constrs/pin.xdc
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/constrs/misc.xdc
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/README.md
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/doc
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/doc/5.2.1-4.png
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/doc/5.2.1-3.png
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/doc/5.2.1-1.png
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/dpu_petalinux_bsp
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/dpu_petalinux_bsp/download_bsp.sh
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/pre-built
./Vitis-AI/dsa/DPU-TRD/prj/Vivado/pre-built/top_wrapper.xsaあ、おそらくここなんだろう。
VitisとVivadoのディレクトリもありますね。
明日はVivadoかVitisのプロジェクトを開いてみます。
まずは、ディレクトリを移動します。
cd ./Vitis-AI/dsa/DPU-TRD/おっと、Vitisの準備を忘れていました。
$ source /opt/Xilinx/Vitis/2020.2/settings64.sh どんなファイルがあるでしょうか？
$ ls
README.md app description.json dpu_ip prjREADME.mdを見ればわかるはず。
$ cat README.md
# Zynq UltraScale+ MPSoC DPU TRD
The Xilinx Deep Learning Processor Unit(DPU) is a configurable computation engine dedicated for convolutional neural networks. The degree of parallelism utilized in the engine is a design parameter and application. It includes a set of highly optimized instructions, and supports most convolutional neural networks, such as VGG, ResNet, GoogleNet, YOLO, SSD, MobileNet, FPN, and others.
### Features
- One AXI salve interface for accessing configuration and status registers.
- One AXI master interface for accessing instructions.
- Supports configurable AXI master interface with 64 or 128 bits for accessing data depending on the target device.
- Supports individual configuration of each channel.
- Supports optional interrupt requeset generation.
- Some highlights of DPU functionality include:
- Configurable hardware architecture includes: B512, B800, B1024, B1152, B1600, B2304, B3136, and B4096
- Maximum of three cores
- Convolution and deconvolution
- Depthwise convolution
- Max poolling
- Average poolling
- ReLU, RELU6, and Leaky ReLU
- Concat
- Elementwise-sum
- Dilation
- Reorg
- Fully connected layer
- Softmax
- Bach Normalization
- Split
### Hardware Architecture
The detailed hardware architecture of the DPU is shown in the following figure. After start-up, the DPU fetches instructions from off-chip memory to control the operation of the computing engine. The instructions are generated by the DNNC where substantial optimizations have been performed. On-chip memory is used to buffer input, intermediate, and output data to achieve high throughput and efficiency. The data is reused as much as possible to reduce the memory bandwidth. A deep pipelined design is used for the computing engine. The processing elements (PE) take full advantage of the finegrained building blocks such as multipliers, adders and accumulators in Xilinx devices.
There are three dimensions of parallelism in the DPU convolution architecture - pixel parallelism, input channel parallelism, and output channel parallelism. The input channel parallelism is always equal to the output channel parallelism. The different architectures require different programmable logic resources. The larger architectures can achieve higher performance with more resources. The parallelism for the different architectures is listed in the table.
|Connolution Architecture|Pixel Parallelism(PP)|Input Channel Parallelism(ICP)|Output Channel Parallelism(OCP)|Peak(operations/per clock)|
|:---|:---|:---|:---|:---|
|B512|4|8|8|512|
|B800|4|10|10|800|
|B1024|8|8|8|1024|
|B1152|4|12|12|1152|
|B1600|8|10|10|1600|
|B2304|8|12|12|2304|
|B3136|8|14|14|3136|
|B4096|8|16|16|4096|
****
[DPU TRD Vitis Flow ](./prj/Vitis/README.md)
[DPU TRD Vivado Flow](./prj/Vivado/README.md)
****うんうん、いい感じなのかな？
./prj/Vivado/README.mdを見ればなにかわかりそうです。
$ cd prj/Vivado/
$ ls
README.md constrs doc dpu_petalinux_bsp pre-built scriptsいい線にきたようです。
README.mdを読もう。
$ cat README.md
# Zynq UltraScale＋ MPSoC DPU TRD V3.3 Vivado 2020.2
## Table of Contents
- [1 Revision History](#1-revision-history)
- [2 Overview](#2-overview)
- [3 Software Tools and System Requirements](#3-software-tools-and-system-requirements)
- [3.1 Hardware](#31-hardware)
- [3.2 Software](#32-software)
- [4 Design Files](#4-design-files)
- [Design Components](#design-components)
- [5 Tutorials](#5-tutorials)
- [5.1 Board Setup](#51-board-setup)
- [5.2 Build and Run TRD Flow](#52-build-and-run-trd-flow)
- [5.2.1 Build the Hardware Design](#521-build-the-hardware-design)
- [5.2.2 Get Json File](#522-get-json-file)
- [5.2.3 DPU PetaLinux BSP](#523-dpu-petalinux-bsp)
- [5.2.4 Run Resnet50 Example](#524-run-resnet50-example)
- [5.3 Configurate the DPU](#53-configurate-the-dpu)
- [5.3.1 Modify the Frequency](#531-modify-the-frequency)
- [5.3.2 Modify the Parameters](#532-modify-the-parameters)
- [6 Run with Vitis AI Library](#6-run-with-vitis-ai-library)
- [7 Known issues](#7-known-issues)
...以下、略README.mdが長い。
読むと面倒くさいので明日にする。
Tweet write: 2021/01/14/ 00:00:00