SymbiFlowをやってみた

もう、10月も終わりに近づいてきた。

最近はなにもやってないのでつぶやくことも少なくなってきた。

久々にメモリしておきたい作業を行ったので備忘録を示しておく。

SymbiFlowをいうFPGAのツールを試してみた。

詳細は・・・

詳細は下記のURLを参照すると良い。

https://symbiflow.github.io/index.html

サンプル

下記のリポジトリをcloneしてサンプルを動かしてみる。

https://github.com/SymbiFlow/symbiflow-examples

サンプルで合成できるデバイスは次の2つである。

  • QuickLogic EOS S3
  • Xilinx 7 series

今回、試したのはもちろん、Xilinx 7 seriesです。

ARTY 35、ARTY 100、BASYS3のサンプルが用意されている。

手元にARTY 100があるので合成してみた。

実行するのはhttps://github.com/SymbiFlow/symbiflow-examplesに記載されていること、そのままである。

手順

まずはcloneする。

$ git clone https://github.com/SymbiFlow/symbiflow-examples.git && cd symbiflow-examples
Cloning into 'symbiflow-examples'...
remote: Enumerating objects: 103, done.
remote: Counting objects: 100% (103/103), done.
remote: Compressing objects: 100% (63/63), done.
remote: Total 408 (delta 59), reused 75 (delta 40), pack-reused 305
Receiving objects: 100% (408/408), 4.28 MiB | 6.25 MiB/s, done.
Resolving deltas: 100% (190/190), done.

次にインストールである。

$ wget https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh -O conda_installer.sh
--2020-10-24 22:10:04--  https://repo.continuum.io/miniconda/Miniconda3-latest-Linux-x86_64.sh
repo.continuum.io (repo.continuum.io) をDNSに問いあわせています... 2606:4700::6812:c94f, 2606:4700::6812:c84f, 104.18.201.79, ...
repo.continuum.io (repo.continuum.io)|2606:4700::6812:c94f|:443 に接続しています... 接続しました。
HTTP による接続要求を送信しました、応答を待っています... 301 Moved Permanently
場所: https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh [続く]
--2020-10-24 22:10:04--  https://repo.anaconda.com/miniconda/Miniconda3-latest-Linux-x86_64.sh
repo.anaconda.com (repo.anaconda.com) をDNSに問いあわせています... 2606:4700::6810:8303, 2606:4700::6810:8203, 104.16.131.3, ...
repo.anaconda.com (repo.anaconda.com)|2606:4700::6810:8303|:443 に接続しています... 接続しました。
HTTP による接続要求を送信しました、応答を待っています... 200 OK
長さ: 93052469 (89M) [application/x-sh]
`conda_installer.sh' に保存中

conda_installer.sh  100%[===================>]  88.74M  89.0MB/s    in 1.0s    

2020-10-24 22:10:06 (89.0 MB/s) - `conda_installer.sh' へ保存完了 [93052469/93052469]

$ INSTALL_DIR=~/opt/symbiflow
$ bash conda_installer.sh -b -p $INSTALL_DIR/xc7/conda
PREFIX=/home/hidemi/opt/symbiflow/xc7/conda
Unpacking payload ...
Collecting package metadata (current_repodata.json): done                       
Solving environment: done

## Package Plan ##

  environment location: /home/hidemi/opt/symbiflow/xc7/conda

  added / updated specs:
    - _libgcc_mutex==0.1=main
    - ca-certificates==2020.1.1=0
    - certifi==2020.4.5.1=py38_0
    - cffi==1.14.0=py38he30daa8_1
    - chardet==3.0.4=py38_1003
    - conda-package-handling==1.6.1=py38h7b6447c_0
    - conda==4.8.3=py38_0
    - cryptography==2.9.2=py38h1ba5d50_0
    - idna==2.9=py_1
    - ld_impl_linux-64==2.33.1=h53a641e_7
    - libedit==3.1.20181209=hc058e9b_0
    - libffi==3.3=he6710b0_1
    - libgcc-ng==9.1.0=hdf63c60_0
    - libstdcxx-ng==9.1.0=hdf63c60_0
    - ncurses==6.2=he6710b0_1
    - openssl==1.1.1g=h7b6447c_0
    - pip==20.0.2=py38_3
    - pycosat==0.6.3=py38h7b6447c_1
    - pycparser==2.20=py_0
    - pyopenssl==19.1.0=py38_0
    - pysocks==1.7.1=py38_0
    - python==3.8.3=hcff3b4d_0
    - readline==8.0=h7b6447c_0
    - requests==2.23.0=py38_0
    - ruamel_yaml==0.15.87=py38h7b6447c_0
    - setuptools==46.4.0=py38_0
    - six==1.14.0=py38_0
    - sqlite==3.31.1=h62c20be_1
    - tk==8.6.8=hbc83047_0
    - tqdm==4.46.0=py_0
    - urllib3==1.25.8=py38_0
    - wheel==0.34.2=py38_0
    - xz==5.2.5=h7b6447c_0
    - yaml==0.1.7=had09818_2
    - zlib==1.2.11=h7b6447c_3

The following NEW packages will be INSTALLED:

  _libgcc_mutex      pkgs/main/linux-64::_libgcc_mutex-0.1-main
  ca-certificates    pkgs/main/linux-64::ca-certificates-2020.1.1-0
  certifi            pkgs/main/linux-64::certifi-2020.4.5.1-py38_0
  cffi               pkgs/main/linux-64::cffi-1.14.0-py38he30daa8_1
  chardet            pkgs/main/linux-64::chardet-3.0.4-py38_1003
  conda              pkgs/main/linux-64::conda-4.8.3-py38_0
  conda-package-han~ pkgs/main/linux-64::conda-package-handling-1.6.1-py38h7b6447c_0
  cryptography       pkgs/main/linux-64::cryptography-2.9.2-py38h1ba5d50_0
  idna               pkgs/main/noarch::idna-2.9-py_1
  ld_impl_linux-64   pkgs/main/linux-64::ld_impl_linux-64-2.33.1-h53a641e_7
  libedit            pkgs/main/linux-64::libedit-3.1.20181209-hc058e9b_0
  libffi             pkgs/main/linux-64::libffi-3.3-he6710b0_1
  libgcc-ng          pkgs/main/linux-64::libgcc-ng-9.1.0-hdf63c60_0
  libstdcxx-ng       pkgs/main/linux-64::libstdcxx-ng-9.1.0-hdf63c60_0
  ncurses            pkgs/main/linux-64::ncurses-6.2-he6710b0_1
  openssl            pkgs/main/linux-64::openssl-1.1.1g-h7b6447c_0
  pip                pkgs/main/linux-64::pip-20.0.2-py38_3
  pycosat            pkgs/main/linux-64::pycosat-0.6.3-py38h7b6447c_1
  pycparser          pkgs/main/noarch::pycparser-2.20-py_0
  pyopenssl          pkgs/main/linux-64::pyopenssl-19.1.0-py38_0
  pysocks            pkgs/main/linux-64::pysocks-1.7.1-py38_0
  python             pkgs/main/linux-64::python-3.8.3-hcff3b4d_0
  readline           pkgs/main/linux-64::readline-8.0-h7b6447c_0
  requests           pkgs/main/linux-64::requests-2.23.0-py38_0
  ruamel_yaml        pkgs/main/linux-64::ruamel_yaml-0.15.87-py38h7b6447c_0
  setuptools         pkgs/main/linux-64::setuptools-46.4.0-py38_0
  six                pkgs/main/linux-64::six-1.14.0-py38_0
  sqlite             pkgs/main/linux-64::sqlite-3.31.1-h62c20be_1
  tk                 pkgs/main/linux-64::tk-8.6.8-hbc83047_0
  tqdm               pkgs/main/noarch::tqdm-4.46.0-py_0
  urllib3            pkgs/main/linux-64::urllib3-1.25.8-py38_0
  wheel              pkgs/main/linux-64::wheel-0.34.2-py38_0
  xz                 pkgs/main/linux-64::xz-5.2.5-h7b6447c_0
  yaml               pkgs/main/linux-64::yaml-0.1.7-had09818_2
  zlib               pkgs/main/linux-64::zlib-1.2.11-h7b6447c_3

Preparing transaction: done
Executing transaction: done
installation finished.
$ source "$INSTALL_DIR/xc7/conda/etc/profile.d/conda.sh"
$ conda env create -f xc7/environment.yml
Collecting package metadata (repodata.json): done
Solving environment: done

==> WARNING: A newer version of conda exists. <==
  current version: 4.8.3
  latest version: 4.9.0

Please update conda by running

    $ conda update -n base -c defaults conda

Downloading and Extracting Packages
make-4.2.1           | 415 KB    | ##################################### | 100% 
git-2.23.0           | 3.2 MB    | ##################################### | 100% 
openssl-1.1.1h       | 2.5 MB    | ##################################### | 100% 
libxml2-2.9.10       | 1.3 MB    | ##################################### | 100% 
symbiflow-yosys-plug | 1.2 MB    | ##################################### | 100% 
prjxray-db-0.0_0232_ | 10.7 MB   | ##################################### | 100% 
certifi-2020.6.20    | 156 KB    | ##################################### | 100% 
pcre-8.44            | 212 KB    | ##################################### | 100% 
tk-8.6.10            | 3.0 MB    | ##################################### | 100% 
sortedcontainers-2.2 | 29 KB     | ##################################### | 100% 
krb5-1.18.2          | 1.3 MB    | ##################################### | 100% 
sqlite-3.33.0        | 1.1 MB    | ##################################### | 100% 
libxslt-1.1.34       | 432 KB    | ##################################### | 100% 
libcurl-7.71.1       | 305 KB    | ##################################### | 100% 
python-3.8.5         | 49.3 MB   | ##################################### | 100% 
lxml-4.6.1           | 1.3 MB    | ##################################### | 100% 
tbb-2020.3           | 1.1 MB    | ##################################### | 100% 
simplejson-3.17.2    | 103 KB    | ##################################### | 100% 
symbiflow-yosys-0.8_ | 10.7 MB   | ##################################### | 100% 
libffi-3.3           | 50 KB     | ##################################### | 100% 
pip-20.2.4           | 1.7 MB    | ##################################### | 100% 
libedit-3.1.20191231 | 116 KB    | ##################################### | 100% 
setuptools-50.3.0    | 714 KB    | ##################################### | 100% 
intervaltree-3.1.0   | 26 KB     | ##################################### | 100% 
symbiflow-vtr-8.0.0. | 57.5 MB   | ##################################### | 100% 
expat-2.2.10         | 153 KB    | ##################################### | 100% 
libssh2-1.9.0        | 269 KB    | ##################################### | 100% 
wheel-0.35.1         | 37 KB     | ##################################### | 100% 
ca-certificates-2020 | 121 KB    | ##################################### | 100% 
prjxray-tools-0.1_26 | 1.2 MB    | ##################################### | 100% 
perl-5.26.2          | 10.5 MB   | ##################################### | 100% 
icu-58.2             | 10.5 MB   | ##################################### | 100% 
Preparing transaction: done
Verifying transaction: done
Executing transaction: done
Ran pip subprocess with arguments:
['/home/hidemi/opt/symbiflow/xc7/conda/envs/xc7/bin/python', '-m', 'pip', 'install', '-U', '-r', '/home/hidemi/workspace/symbiflow/symbiflow-examples/xc7/condaenv.0vgew8cw.requirements.txt']
Pip subprocess output:
Collecting git+https://github.com/symbiflow/fasm (from -r file:requirements.txt (line 2))
  Cloning https://github.com/symbiflow/fasm to /tmp/pip-req-build-2g17fqbp
Collecting git+https://github.com/symbiflow/xc-fasm (from -r file:requirements.txt (line 3))
  Cloning https://github.com/symbiflow/xc-fasm to /tmp/pip-req-build-__9x9wng
Processing /home/hidemi/.cache/pip/wheels/86/ba/5c/4e9115777de42c6a2e1ca77ef7c9d0d479254c5080341b55c5/python_constraint-1.4.0-py2.py3-none-any.whl
Collecting textx
  Using cached textX-2.2.0-py2.py3-none-any.whl (65 kB)
Requirement already satisfied, skipping upgrade: intervaltree in /home/hidemi/opt/symbiflow/xc7/conda/envs/xc7/lib/python3.8/site-packages (from xc-fasm==0.0.1->-r file:requirements.txt (line 3)) (3.1.0)
Requirement already satisfied, skipping upgrade: simplejson in /home/hidemi/opt/symbiflow/xc7/conda/envs/xc7/lib/python3.8/site-packages (from xc-fasm==0.0.1->-r file:requirements.txt (line 3)) (3.17.2)
Collecting prjxray@ git+git://github.com/SymbiFlow/prjxray.git#egg=prjxray
  Cloning git://github.com/SymbiFlow/prjxray.git to /tmp/pip-install-9z4mep5p/prjxray
Collecting Arpeggio>=1.9.0
  Using cached Arpeggio-1.9.2-py2.py3-none-any.whl (57 kB)
Collecting click<8.0,>=7.0
  Using cached click-7.1.2-py2.py3-none-any.whl (82 kB)
Requirement already satisfied, skipping upgrade: sortedcontainers<3.0,>=2.0 in /home/hidemi/opt/symbiflow/xc7/conda/envs/xc7/lib/python3.8/site-packages (from intervaltree->xc-fasm==0.0.1->-r file:requirements.txt (line 3)) (2.2.2)
Building wheels for collected packages: fasm, xc-fasm, prjxray
  Building wheel for fasm (setup.py): started
  Building wheel for fasm (setup.py): finished with status 'done'
  Created wheel for fasm: filename=fasm-0.0.1-py2.py3-none-any.whl size=8231 sha256=5471ee752aa3484c96f761dc1ed601b7abf3b3907293b9c2fa87ef8042240b05
  Stored in directory: /tmp/pip-ephem-wheel-cache-4f17y56t/wheels/99/13/30/83ebd1452c46e01b4533e202afb18931341abc56685f541936
  Building wheel for xc-fasm (setup.py): started
  Building wheel for xc-fasm (setup.py): finished with status 'done'
  Created wheel for xc-fasm: filename=xc_fasm-0.0.1-py3-none-any.whl size=5915 sha256=720cee59af29fc32411a97a73edef2eebd802bcc7a800daade52d15f3981e5a9
  Stored in directory: /tmp/pip-ephem-wheel-cache-4f17y56t/wheels/2f/3e/2e/3422d3bfce5a1c8e340d718c8f8cb3bcec00bb484cb27a8f6c
  Building wheel for prjxray (setup.py): started
  Building wheel for prjxray (setup.py): finished with status 'done'
  Created wheel for prjxray: filename=prjxray-0.0.1-py3-none-any.whl size=57716 sha256=ca50f9216badee5b1d0ff3d8e1c1ed7879286329ae8ebc219cfe5de4332eb49c
  Stored in directory: /tmp/pip-ephem-wheel-cache-4f17y56t/wheels/c2/38/92/714737988a05df2e6cd1e426dfc077379709a2a40fa6666d88
Successfully built fasm xc-fasm prjxray
Installing collected packages: python-constraint, Arpeggio, click, textx, fasm, prjxray, xc-fasm
Successfully installed Arpeggio-1.9.2 click-7.1.2 fasm-0.0.1 prjxray-0.0.1 python-constraint-1.4.0 textx-2.2.0 xc-fasm-0.0.1

#
# To activate this environment, use
#
#     $ conda activate xc7
#
# To deactivate an active environment, use
#
#     $ conda deactivate

$ conda activate xc7
(xc7) $ wget -qO- https://storage.googleapis.com/symbiflow-arch-defs/artifacts/prod/foss-fpga-tools/symbiflow-arch-defs/continuous/install/66/20200914-111752/symbiflow-arch-defs-install-05d68df0.tar.xz | tar -xJ --one-top-level=$INSTALL_DIR/xc7/install
(xc7) $ conda deactivate

ここからが合成である。

$ export INSTALL_DIR=~/opt/symbiflow
$ export PATH="$INSTALL_DIR/xc7/install/bin:$PATH"
$ source "$INSTALL_DIR/xc7/conda/etc/profile.d/conda.sh"
$ conda activate xc7
(xc7) $ pushd xc7/counter_test && make clean && TARGET="arty_100" make && popd
~/workspace/symbiflow/symbiflow-examples/xc7/counter_test ~/workspace/symbiflow/symbiflow-examples ~/workspace/symbiflow ~
rm -rf build
mkdir build
cd build && symbiflow_synth -t top -v /home/hidemi/workspace/symbiflow/symbiflow-examples/xc7/counter_test/counter.v -d artix7 -p xc7a100tcsg324-1 2>&1 > /dev/null
cd build && symbiflow_pack -e top.eblif -d xc7a100t_test -s /home/hidemi/workspace/symbiflow/symbiflow-examples/xc7/counter_test/counter.sdc 2>&1 > /dev/null
cd build && symbiflow_place -e top.eblif -d xc7a100t_test -p /home/hidemi/workspace/symbiflow/symbiflow-examples/xc7/counter_test/arty.pcf -n top.net -P xc7a100tcsg324-1 -s /home/hidemi/workspace/symbiflow/symbiflow-examples/xc7/counter_test/counter.sdc 2>&1 > /dev/null
cd build && symbiflow_route -e top.eblif -d xc7a100t_test -s /home/hidemi/workspace/symbiflow/symbiflow-examples/xc7/counter_test/counter.sdc 2>&1 > /dev/null
cd build && symbiflow_write_fasm -e top.eblif -d xc7a100t_test
Using default VPR options.
VPR FPGA Placement and Routing.
Version: 8.1.0-dev+8980e4621
Revision: v8.0.0.rc2-4003-g8980e4621
Compiled: 2020-09-02T12:00:44
Compiler: GNU 7.3.0 on Linux-4.15.0-1077-gcp x86_64
Build Info: Release IPO VTR_ASSERT_LEVEL=2

University of Toronto
verilogtorouting.org
vtr-users@googlegroups.com
This is free open source code under MIT license.

VPR was run with the following command-line:
genfasm /home/hidemi/opt/symbiflow/xc7/install/share/symbiflow/arch/xc7a100t_test/arch.timing.xml top.eblif --device xc7a100t-test --max_router_iterations 500 --routing_failure_predictor off --router_high_fanout_threshold -1 --constant_net_method route --route_chan_width 500 --router_heap bucket --clock_modeling route --place_delta_delay_matrix_calculation_method dijkstra --place_delay_model delta_override --router_lookahead connection_box_map --check_route quick --strict_checks off --allow_dangling_combinational_nodes on --disable_errors check_unbuffered_edges:check_route --congested_routing_iteration_threshold 0.8 --incremental_reroute_delay_ripup off --base_cost_type delay_normalized_length_bounded --bb_factor 10 --initial_pres_fac 4.0 --check_rr_graph off --suppress_warnings ,sum_pin_class:check_unbuffered_edges:load_rr_indexed_data_T_values:check_rr_node:trans_per_R:check_route:set_rr_graph_tool_comment:calculate_average_switch --read_rr_graph /home/hidemi/opt/symbiflow/xc7/install/share/symbiflow/arch/xc7a100t_test/rr_graph_xc7a100t_test.rr_graph.real.bin

Using up to 1 parallel worker(s)

Architecture file: /home/hidemi/opt/symbiflow/xc7/install/share/symbiflow/arch/xc7a100t_test/arch.timing.xml
Circuit name: top

Loading Architecture Description
Warning 1: Model 'CE_VCC' output port 'VCC' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 2: Model 'SR_GND' output port 'GND' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 3: Model 'NO_FF' input port 'D' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 4: Model 'NO_DRAM' input port 'A' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 5: Model 'RAMB18E1_VPR' input port 'ADDRBTIEHIGH' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 6: Model 'RAMB18E1_VPR' input port 'ADDRATIEHIGH' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 7: Model 'RAMB36E1_PRIM' input port 'CASCADEINB' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 8: Model 'RAMB36E1_PRIM' input port 'CASCADEINA' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 9: Model 'RAMB36E1_PRIM' output port 'CASCADEOUTB' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 10: Model 'RAMB36E1_PRIM' output port 'CASCADEOUTA' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 11: Model 'IDELAYE2_VPR' input port 'LDPIPEEN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 12: Model 'IDELAYE2_VPR' input port 'IDATAIN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 13: Model 'IDELAYE2_VPR' input port 'DATAIN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 14: Model 'IDELAYE2_VPR' input port 'CNTVALUEIN4' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 15: Model 'IDELAYE2_VPR' input port 'CNTVALUEIN3' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 16: Model 'IDELAYE2_VPR' input port 'CNTVALUEIN2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 17: Model 'IDELAYE2_VPR' input port 'CNTVALUEIN1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 18: Model 'IDELAYE2_VPR' input port 'CNTVALUEIN0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 19: Model 'IDELAYE2_VPR' input port 'CINVCTRL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 20: Model 'IDELAYE2_VPR' output port 'DATAOUT' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 21: Model 'IDELAYE2_VPR' output port 'CNTVALUEOUT4' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 22: Model 'IDELAYE2_VPR' output port 'CNTVALUEOUT3' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 23: Model 'IDELAYE2_VPR' output port 'CNTVALUEOUT2' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 24: Model 'IDELAYE2_VPR' output port 'CNTVALUEOUT1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 25: Model 'IDELAYE2_VPR' output port 'CNTVALUEOUT0' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 26: Model 'ISERDESE2_NO_IDELAY_VPR' input port 'SHIFTIN2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 27: Model 'ISERDESE2_NO_IDELAY_VPR' input port 'SHIFTIN1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 28: Model 'ISERDESE2_NO_IDELAY_VPR' input port 'DYNCLKSEL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 29: Model 'ISERDESE2_NO_IDELAY_VPR' input port 'DYNCLKDIVSEL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 30: Model 'ISERDESE2_NO_IDELAY_VPR' input port 'DYNCLKDIVPSEL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 31: Model 'ISERDESE2_NO_IDELAY_VPR' output port 'SHIFTOUT2' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 32: Model 'ISERDESE2_NO_IDELAY_VPR' output port 'SHIFTOUT1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 33: Model 'ISERDESE2_IDELAY_VPR' input port 'SHIFTIN2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 34: Model 'ISERDESE2_IDELAY_VPR' input port 'SHIFTIN1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 35: Model 'ISERDESE2_IDELAY_VPR' input port 'DYNCLKSEL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 36: Model 'ISERDESE2_IDELAY_VPR' input port 'DYNCLKDIVSEL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 37: Model 'ISERDESE2_IDELAY_VPR' input port 'DYNCLKDIVPSEL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 38: Model 'ISERDESE2_IDELAY_VPR' output port 'SHIFTOUT2' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 39: Model 'ISERDESE2_IDELAY_VPR' output port 'SHIFTOUT1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 40: Model 'IDDR_VPR' input port 'SR' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 41: Model 'OSERDESE2_VPR' input port 'SHIFTIN2' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 42: Model 'OSERDESE2_VPR' input port 'SHIFTIN1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 43: Model 'OSERDESE2_VPR' input port 'TBYTEIN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 44: Model 'OSERDESE2_VPR' output port 'SHIFTOUT2' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 45: Model 'OSERDESE2_VPR' output port 'SHIFTOUT1' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 46: Model 'ODDR_VPR' input port 'SR' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 47: Model 'BUFGCTRL_VPR' input port 'S1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 48: Model 'BUFGCTRL_VPR' input port 'S0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 49: Model 'BUFGCTRL_VPR' input port 'IGNORE1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 50: Model 'BUFGCTRL_VPR' input port 'IGNORE0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 51: Model 'BUFGCTRL_VPR' input port 'CE1' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 52: Model 'BUFGCTRL_VPR' input port 'CE0' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 53: Model 'PLLE2_ADV_VPR' input port 'PWRDWN' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 54: Model 'PLLE2_ADV_VPR' input port 'CLKINSEL' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 55: Model 'IDELAYCTRL' input port 'RST' has no timing specification (no clock specified to create a sequential input port, not combinationally connected to any outputs, not a clock input)
Warning 56: Model 'IDELAYCTRL' output port 'RDY' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 57: Model 'VCC' output port 'VCC' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 58: Model 'GND' output port 'GND' has no timing specification (no clock specified to create a sequential output port, not combinationally connected to any inputs, not a clock output)
Warning 59: <pb_type> 'empty' timing-annotation/<model> mismatch on port 'D' of model '.latch', port is a sequential input but has neither T_setup nor T_hold specified
Warning 60: <pb_type> 'empty' timing-annotation/<model> mismatch on port 'Q' of model '.latch', port is a sequential output but has neither min nor max T_clock_to_Q specified
Loading Architecture Description took 0.16 seconds (max_rss 35.3 MiB, delta_rss +29.3 MiB)
Warning 61: Non-zero switch output capacitance (4e-15) has no effect when switch 'buffer' is used for connection block inputs
Building complex block graph
Building complex block graph took 0.01 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Load circuit
Load circuit took 0.00 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Clean circuit
Absorbed 0 LUT buffers
Inferred   55 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred    5 additional primitive pins as constant generators due to constant inputs
Inferred    0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred    0 additional primitive pins as constant generators due to constant inputs
Inferred    0 additional primitive pins as constant generators since they have no combinationally connected inputs
Inferred    0 additional primitive pins as constant generators due to constant inputs
Swept input(s)      : 0
Swept output(s)     : 0 (0 dangling, 0 constant)
Swept net(s)        : 33
Swept block(s)      : 1
Constant Pins Marked: 60
Clean circuit took 0.00 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Compress circuit
Compress circuit took 0.00 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Verify circuit
Verify circuit took 0.00 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Circuit Statistics:
  Blocks: 108
    .input      :       2
    .output     :       5
    5-LUT       :       1
    BUFGCTRL_VPR:       1
    CARRY4_VPR  :       7
    CE_VCC      :      26
    FDRE_ZINI   :      26
    GND         :       1
    IBUF_VPR    :       2
    OBUFT_VPR   :       5
    SR_GND      :      26
    T_INV       :       5
    VCC         :       1
  Nets  : 127
    Avg Fanout:     1.6
    Max Fanout:    29.0
    Min Fanout:     1.0
  Netlist Clocks: 2
Build Timing Graph
Warning 62: Inferred implicit clock source $iopadmap$top.clk.O[0] for netlist clock $abc$2141$iopadmap$clk (possibly data used as clock)
Warning 63: Timing edge from $iopadmap$top.clk.I[0] to $iopadmap$top.clk.O[0] will not be created since $iopadmap$top.clk.O[0] has been identified as a clock generator
  Timing Graph Nodes: 324
  Timing Graph Edges: 492
  Timing Graph Levels: 20
Build Timing Graph took 0.00 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Netlist contains 2 clocks
  Netlist Clock '$abc$2141$iopadmap$clk' Fanout: 1 pins (0.3%), 1 blocks (0.9%)
  Netlist Clock 'bufg' Fanout: 26 pins (8.0%), 26 blocks (24.1%)
Load Timing Constraints

SDC file 'top.sdc' not found
Setting default timing constraints:
   * constrain all primay inputs and primary outputs on a virtual external clock 'virtual_io_clock'
   * optimize all netlist and virtual clocks to run as fast as possible
   * ignore cross netlist clock domain timing paths
Timing constraints created 3 clocks
  Constrained Clock 'virtual_io_clock' (Virtual Clock)
  Constrained Clock '$abc$2141$iopadmap$clk' Source: '$iopadmap$top.clk.O[0]'
  Constrained Clock 'bufg' Source: 'bufgctrl.O[0]'

Load Timing Constraints took 0.00 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Timing analysis: ON
Circuit netlist file: top.net
Circuit placement file: top.place
Circuit routing file: top.route
Circuit SDC file: top.sdc

Packer: ENABLED
Placer: ENABLED
Router: ENABLED
Analysis: ENABLED

NetlistOpts.abosrb_buffer_luts            : true
NetlistOpts.sweep_dangling_primary_ios    : true
NetlistOpts.sweep_dangling_nets           : true
NetlistOpts.sweep_dangling_blocks         : true
NetlistOpts.sweep_constant_primary_outputs: false

PackerOpts.allow_unrelated_clustering: auto
PackerOpts.alpha_clustering: 0.750000
PackerOpts.beta_clustering: 0.900000
PackerOpts.cluster_seed_type: BLEND2
PackerOpts.connection_driven: true
PackerOpts.global_clocks: true
PackerOpts.hill_climbing_flag: false
PackerOpts.inter_cluster_net_delay: 1.000000
PackerOpts.timing_driven: true
PackerOpts.target_external_pin_util: auto
PlacerOpts.place_freq: PLACE_ONCE
PlacerOpts.place_algorithm: PATH_TIMING_DRIVEN_PLACE
PlacerOpts.pad_loc_type: FREE
PlacerOpts.place_cost_exp: 1.000000
PlacerOpts.place_chan_width: 500
PlacerOpts.inner_loop_recompute_divider: 0
PlacerOpts.recompute_crit_iter: 1
PlacerOpts.timing_tradeoff: 0.500000
PlacerOpts.td_place_exp_first: 1.000000
PlacerOpts.td_place_exp_last: 8.000000
PlaceOpts.seed: 1
AnnealSched.type: AUTO_SCHED
AnnealSched.inner_num: 1.000000

RouterOpts.route_type: DETAILED
RouterOpts.router_algorithm: TIMING_DRIVEN
RouterOpts.base_cost_type: DELAY_NORMALIZED_LENGTH_BOUNDED
RouterOpts.fixed_channel_width: 500
RouterOpts.trim_empty_chan: false
RouterOpts.trim_obs_chan: false
RouterOpts.acc_fac: 1.000000
RouterOpts.bb_factor: 10
RouterOpts.bend_cost: 0.000000
RouterOpts.first_iter_pres_fac: 0.000000
RouterOpts.initial_pres_fac: 4.000000
RouterOpts.pres_fac_mult: 1.300000
RouterOpts.max_router_iterations: 500
RouterOpts.min_incremental_reroute_fanout: 16
RouterOpts.astar_fac: 1.200000
RouterOpts.criticality_exp: 1.000000
RouterOpts.max_criticality: 0.990000
RouterOpts.routing_failure_predictor = OFF
RouterOpts.routing_budgets_algorithm = DISABLE

AnalysisOpts.gen_post_synthesis_netlist: false

RoutingArch.directionality: BI_DIRECTIONAL
RoutingArch.switch_block_type: WILTON
RoutingArch.Fs: 3

Load Packing
Begin loading packed FPGA netlist file.
Netlist generated from file 'top.net'.
Detected 54 constant generators (to see names run with higher pack verbosity)
Finished loading packed FPGA netlist file (took 0.012302 seconds).
Load Packing took 0.01 seconds (max_rss 35.3 MiB, delta_rss +0.0 MiB)
Warning 64: Netlist contains 0 global net to non-global architecture pin connections
Warning 65: Logic block #15 ($false) has only 1 input pin '$false.GND[0]' -- the whole block is hanging logic that should be swept.
Warning 66: Logic block #16 ($true) has only 1 input pin '$true.VCC[0]' -- the whole block is hanging logic that should be swept.

Netlist num_nets: 61
Netlist num_blocks: 17
Netlist EMPTY blocks: 0.
Netlist BLK-TL-SLICEL blocks: 7.
Netlist BLK-TL-SLICEM blocks: 0.
Netlist BLK-TL-BRAM_L blocks: 0.
Netlist BLK-TL-IOPAD blocks: 7.
Netlist BLK-TL-IOPAD_M blocks: 0.
Netlist BLK-TL-IOPAD_S blocks: 0.
Netlist BLK-TL-BUFGCTRL blocks: 1.
Netlist BLK-TL-PLLE2_ADV blocks: 0.
Netlist BLK-TL-HCLK_IOI3 blocks: 0.
Netlist SYN-VCC blocks: 1.
Netlist SYN-GND blocks: 1.
Netlist inputs pins: 2
Netlist output pins: 10

Pb types usage...
  BLK-TL-SLICEL              : 7
   SLICEL0                   : 7
    COMMON_LUT_AND_F78MUX    : 1
     ALUT                    : 1
      A5LUT                  : 1
       lut                   : 1
    COMMON_SLICE             : 7
     CARRY4_VPR              : 7
     CEUSEDMUX               : 7
      CE_VCC                 : 26
     SLICE_FF                : 7
      REG_FDSE_or_FDRE       : 26
       FDRE                  : 26
     SRUSEDMUX               : 7
      SR_GND                 : 26
  BLK-TL-IOPAD               : 7
   IOB33                     : 7
    IOB33_MODES              : 7
     IBUF_VPR                : 2
     inpad                   : 2
     OBUFT_VPR               : 5
     outpad                  : 5
   OLOGICE3                  : 5
    OLOGIC_TFF               : 5
     T_INV                   : 5
  BLK-TL-BUFGCTRL            : 1
   BUFGCTRL_VPR              : 1
  SYN-VCC                    : 1
   VCC                       : 1
  SYN-GND                    : 1
   GND                       : 1

Create Device
# Build Device Grid
FPGA sized to 150 x 215: 32250 grid tiles (xc7a100t-test)

Resource usage...
    Netlist
        7   blocks of type: BLK-TL-SLICEL
    Architecture
        2950    blocks of type: BLK-TL-CLBLL_L
        3400    blocks of type: BLK-TL-CLBLL_R
        4800    blocks of type: BLK-TL-CLBLM_L
        4700    blocks of type: BLK-TL-CLBLM_R
    Netlist
        0   blocks of type: BLK-TL-SLICEM
    Architecture
        4800    blocks of type: BLK-TL-CLBLM_L
        4700    blocks of type: BLK-TL-CLBLM_R
    Netlist
        0   blocks of type: BLK-TL-BRAM_L
    Architecture
        115 blocks of type: BLK-TL-BRAM_L
    Netlist
        7   blocks of type: BLK-TL-IOPAD
    Architecture
        8   blocks of type: BLK-TL-LIOPAD_SING
        4   blocks of type: BLK-TL-RIOPAD_SING
        96  blocks of type: BLK-TL-LIOPAD_M
        48  blocks of type: BLK-TL-RIOPAD_M
        96  blocks of type: BLK-TL-LIOPAD_S
        48  blocks of type: BLK-TL-RIOPAD_S
    Netlist
        0   blocks of type: BLK-TL-IOPAD_M
    Architecture
        96  blocks of type: BLK-TL-LIOPAD_M
        48  blocks of type: BLK-TL-RIOPAD_M
    Netlist
        0   blocks of type: BLK-TL-IOPAD_S
    Architecture
        96  blocks of type: BLK-TL-LIOPAD_S
        48  blocks of type: BLK-TL-RIOPAD_S
    Netlist
        1   blocks of type: BLK-TL-BUFGCTRL
    Architecture
        16  blocks of type: BLK-TL-CLK_BUFG_BOT_R
        16  blocks of type: BLK-TL-CLK_BUFG_TOP_R
    Netlist
        0   blocks of type: BLK-TL-PLLE2_ADV
    Architecture
        2   blocks of type: BLK-TL-CMT_TOP_L_UPPER_T
        4   blocks of type: BLK-TL-CMT_TOP_R_UPPER_T
    Netlist
        0   blocks of type: BLK-TL-HCLK_IOI3
    Architecture
        6   blocks of type: BLK-TL-HCLK_IOI3
    Netlist
        1   blocks of type: SYN-VCC
    Architecture
        1   blocks of type: SYN-VCC
    Netlist
        1   blocks of type: SYN-GND
    Architecture
        1   blocks of type: SYN-GND

Device Utilization: 0.00 (target 1.00)
    Physical Tile BLK-TL-CLBLL_L:
    Block Utilization: 0.00 Logical Block: BLK-TL-SLICEL
    Physical Tile BLK-TL-CLBLL_R:
    Block Utilization: 0.00 Logical Block: BLK-TL-SLICEL
    Physical Tile BLK-TL-CLBLM_L:
    Block Utilization: 0.00 Logical Block: BLK-TL-SLICEL
    Block Utilization: 0.00 Logical Block: BLK-TL-SLICEM
    Physical Tile BLK-TL-CLBLM_R:
    Block Utilization: 0.00 Logical Block: BLK-TL-SLICEL
    Block Utilization: 0.00 Logical Block: BLK-TL-SLICEM
    Physical Tile BLK-TL-BRAM_L:
    Block Utilization: 0.00 Logical Block: BLK-TL-BRAM_L
    Physical Tile BLK-TL-LIOPAD_M:
    Block Utilization: 0.07 Logical Block: BLK-TL-IOPAD
    Block Utilization: 0.00 Logical Block: BLK-TL-IOPAD_M
    Physical Tile BLK-TL-LIOPAD_S:
    Block Utilization: 0.07 Logical Block: BLK-TL-IOPAD
    Block Utilization: 0.00 Logical Block: BLK-TL-IOPAD_S
    Physical Tile BLK-TL-LIOPAD_SING:
    Block Utilization: 0.88 Logical Block: BLK-TL-IOPAD
    Physical Tile BLK-TL-RIOPAD_M:
    Block Utilization: 0.15 Logical Block: BLK-TL-IOPAD
    Block Utilization: 0.00 Logical Block: BLK-TL-IOPAD_M
    Physical Tile BLK-TL-RIOPAD_S:
    Block Utilization: 0.15 Logical Block: BLK-TL-IOPAD
    Block Utilization: 0.00 Logical Block: BLK-TL-IOPAD_S
    Physical Tile BLK-TL-RIOPAD_SING:
    Block Utilization: 1.75 Logical Block: BLK-TL-IOPAD
    Physical Tile BLK-TL-CLK_BUFG_BOT_R:
    Block Utilization: 0.06 Logical Block: BLK-TL-BUFGCTRL
    Physical Tile BLK-TL-CLK_BUFG_TOP_R:
    Block Utilization: 0.06 Logical Block: BLK-TL-BUFGCTRL
    Physical Tile BLK-TL-CMT_TOP_L_UPPER_T:
    Block Utilization: 0.00 Logical Block: BLK-TL-PLLE2_ADV
    Physical Tile BLK-TL-CMT_TOP_R_UPPER_T:
    Block Utilization: 0.00 Logical Block: BLK-TL-PLLE2_ADV
    Physical Tile BLK-TL-HCLK_IOI3:
    Block Utilization: 0.00 Logical Block: BLK-TL-HCLK_IOI3
    Physical Tile SYN-VCC:
    Block Utilization: 1.00 Logical Block: SYN-VCC
    Physical Tile SYN-GND:
    Block Utilization: 1.00 Logical Block: SYN-GND

# Build Device Grid took 0.05 seconds (max_rss 36.9 MiB, delta_rss +1.5 MiB)
# Loading routing resource graph

# Loading routing resource graph took 20.10 seconds (max_rss 7174.5 MiB, delta_rss +7137.6 MiB)
  RR Graph Nodes: 5433464
  RR Graph Edges: 41271995
Create Device took 21.12 seconds (max_rss 7174.5 MiB, delta_rss +7139.1 MiB)

Load Placement
Load Placement took 0.00 seconds (max_rss 7174.5 MiB, delta_rss +0.0 MiB)

Load Routing
Begin loading FPGA routing file.
Finished loading route file
Load Routing took 0.10 seconds (max_rss 7174.5 MiB, delta_rss +0.0 MiB)

Checking to ensure routing is legal...
Completed routing consistency check successfully.

Serial number (magic cookie) for the routing is: 416897035
Circuit successfully routed with a channel width factor of 500.
Writing Implementation FASM: top.fasm
The entire flow of VPR took 25.4152 seconds.
FASM extra: top_fasm_extra.fasm
cd build && symbiflow_write_bitstream -d artix7 -f top.fasm -p xc7a100tcsg324-1 -b top.bit
Writing bitstream ...
~/workspace/symbiflow/symbiflow-examples ~/workspace/symbiflow ~
(xc7) $ conda deactivate

合成が完了したのでディレクトリを確認する。

$ ls xc7/counter_test/build/
constraints.place                      top.eblif
fasm.log                               top.fasm
pack.log                               top.ioplace
packing_pin_util.rpt                   top.json
place.log                              top.net
pre_pack.report_timing.setup.rpt       top.place
report_timing.hold.rpt                 top.route
report_timing.setup.rpt                top_io.json
report_unconstrained_timing.hold.rpt   top_synth.log
report_unconstrained_timing.setup.rpt  top_synth.v
route.log                              top_synth.v.premap.v
top.bit

top.bitが生成されているのでARTY 100に書き込んでみた。

LEDがインクリメントした。

ちゃんと合成して動作することを確認できた。

write: 2020/10/24/ 21:55:49