ひでみのアイデア帳

くだらないことなんだけど、忘れないために・・・

超苦労してSDSoCやってみた

超苦労って、なんでこんなにトラップが多いのだろ?

本題の開発でトラップに引っかかっているわけではないので、なんだかなぁ〜な気分・・・

Vivadoプロジェクト

プロジェクトをこんな感じ。

DSA作成スクリプト

VivadoでDSAを作成するスクリプトはこんな感じ。

set_property PFM_NAME "custom:ultra96:ultra96:1.0" \
[get_files ultra96.srcs/sources_1/bd/ultra96/ultra96.bd]

set_property PFM.CLOCK { \
clk_out1 {id "0" is_default "false" proc_sys_reset "proc_sys_reset_0" } \
clk_out2 {id "1" is_default "true" proc_sys_reset "proc_sys_reset_1" } \
clk_out3 {id "2" is_default "false" proc_sys_reset "proc_sys_reset_2" } \
clk_out4 {id "3" is_default "false" proc_sys_reset "proc_sys_reset_3" } \
} [get_bd_cells /clk_wiz_0]

set_property PFM.AXI_PORT { \
M_AXI_HPM0_FPD {memport "M_AXI_GP"} \
M_AXI_HPM1_FPD {memport "M_AXI_GP"} \
M_AXI_HPM0_LPD {memport "M_AXI_GP"} \
S_AXI_HPC0_FPD {memport "S_AXI_HPC" sptag "HPC0"} \
S_AXI_HPC1_FPD {memport "S_AXI_HPC" sptag "HPC1"} \
S_AXI_HP0_FPD {memport "S_AXI_HP" sptag "HP0"} \
S_AXI_HP1_FPD {memport "S_AXI_HP" sptag "HP1"} \
} [get_bd_cells /ps_e]

set intVar []
for {set i 0} {$i < 8} {incr i} {
lappend intVar In$i {}
}

set_property PFM.IRQ $intVar [get_bd_cells /xlconcat_0]

generate_target all [get_files ultra96.srcs/sources_1/bd/ultra96/ultra96.bd]

write_dsa ultra96.dsa -force

SDSoCの結果

こんな感じでコンパイルできた。

21:18:11 **** Build of configuration Debug for project sample ****
make pre-build main-build 
sdsoc_make_clean Debug

Building file: ../src/sample.c
Invoking: SDSCC Compiler
sdscc -Wall -O0 -g -I"../src" -c -fmessage-length=0 -MT"src/sample.o" -MMD -MP -MF"src/sample.d" -MT"src/sample.o" -o "src/sample.o" "../src/sample.c" -sds-hw fibo sample.c  -clkid 1 -sds-end -sds-sys-config r5_standalone -sds-proc r5_standalone -sds-pf "/home/hidemi/workspace/Ultra96/sdsoc/ultra96/export/ultra96"
Processing -sds-hw block for fibo
Create data motion intermediate representation
Performing accelerator source linting for fibo
Performing pragma generation
INFO: [PragmaGen 83-3231] Successfully generated tcl script: /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/vhls/fibo.tcl
Moving function fibo to Programmable Logic
sdscc log file saved as /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/reports/sds_sample.log

Finished building: ../src/sample.c

Building target: sample.elf
Invoking: SDS++ Linker
sds++ --remote_ip_cache /home/hidemi/workspace/Ultra96/sdsoc/ip_cache -o "sample.elf"  ./src/sample.o    -dmclkid 1  -sds-sys-config r5_standalone -sds-proc r5_standalone -sds-pf "/home/hidemi/workspace/Ultra96/sdsoc/ultra96/export/ultra96"
Analyzing object files
... /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/src/sample.o
Generating data motion network
INFO: [DMAnalysis 83-4494] Analyzing hardware accelerators...
INFO: [DMAnalysis 83-4497] Analyzing callers to hardware accelerators...
INFO: [DMAnalysis 83-4444] Scheduling data transfer graph for partition 0
INFO: [DMAnalysis 83-4446] Creating data motion network hardware for partition 0
INFO: [DMAnalysis 83-4448] Creating software stub functions for partition 0
INFO: [DMAnalysis 83-4450] Generating data motion network report for partition 0
INFO: [DMAnalysis 83-4454] Rewriting caller code
Creating block diagram (BD)
Creating top.bd.tcl
/opt/Xilinx/SDx/2018.2/bin/cf2xd: 4: /opt/Xilinx/SDx/2018.2/bin/cf2xd: [[: not found
/opt/Xilinx/SDx/2018.2/bin/cf2xd: 4: /opt/Xilinx/SDx/2018.2/bin/cf2xd: [[: not found
/opt/Xilinx/SDx/2018.2/bin/cf_xsd: 4: /opt/Xilinx/SDx/2018.2/bin/cf_xsd: [[: not found
/opt/Xilinx/SDx/2018.2/bin/cf_xsd: 4: /opt/Xilinx/SDx/2018.2/bin/cf_xsd: [[: not found
Rewrite caller functions
Compile caller rewrite file /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/swstubs/sample.c
Prepare hardware access API functions
Create accelerator stub functions
Compile hardware access API functions
Compile accelerator stub functions
Create board support package library
Preliminary link application ELF
Enable generation of hardware programming files
Enable generation of boot files
Calling VPL

****** vpl v2018.2 (64-bit)
  **** SW Build 2258646 on Thu Jun 14 20:02:38 MDT 2018
    ** Copyright 1986-2018 Xilinx, Inc. All Rights Reserved.

Attempting to get a license: ap_opencl
WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ". 
Attempting to get a license: ap_sdsoc
Feature available: ap_sdsoc
INFO: [VPL 60-895]   Target platform: /home/hidemi/workspace/Ultra96/sdsoc/ultra96/export/ultra96/ultra96.xpfm
INFO: [VPL 60-423]   Target device: ultra96
INFO: [VPL 60-1032] Extracting DSA to /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/p0/vivado/.local/dsa
INFO: [VPL 60-251]   Hardware accelerator integration...
Creating Vivado project and starting FPGA synthesis.
[21:22:56] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[21:23:56] Block-level synthesis in progress, 0 of 1 jobs complete, 1 job running.
[21:24:56] Top-level synthesis in progress.
[21:25:56] Top-level synthesis in progress.
[21:29:28] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 10m 13s 

[21:29:28] Starting logic optimization..
[21:29:33] Phase 1 Retarget
[21:29:33] Phase 2 Constant propagation
[21:29:33] Phase 3 Sweep
[21:29:33] Phase 4 BUFG optimization
[21:29:38] Phase 5 Shift Register Optimization
[21:29:38] Phase 6 Post Processing Netlist
[21:29:53] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 00m 25s 

[21:29:53] Starting logic placement..
[21:30:08] Phase 1 Placer Initialization
[21:30:08] Phase 1.1 Placer Initialization Netlist Sorting
[21:30:08] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[21:30:39] Phase 1.3 Build Placer Netlist Model
[21:30:39] Phase 1.4 Constrain Clocks/Macros
[21:30:39] Phase 2 Global Placement
[21:30:39] Phase 2.1 Floorplanning
[21:30:49] Phase 2.2 Physical Synthesis In Placer
[21:30:54] Phase 3 Detail Placement
[21:30:54] Phase 3.1 Commit Multi Column Macros
[21:30:54] Phase 3.2 Commit Most Macros & LUTRAMs
[21:30:54] Phase 3.3 Area Swap Optimization
[21:30:54] Phase 3.4 Pipeline Register Optimization
[21:30:54] Phase 3.5 Small Shape Clustering
[21:30:54] Phase 3.6 DP Optimization
[21:30:59] Phase 3.7 Flow Legalize Slice Clusters
[21:30:59] Phase 3.8 Slice Area Swap
[21:30:59] Phase 3.9 Commit Slice Clusters
[21:30:59] Phase 3.10 Re-assign LUT pins
[21:30:59] Phase 3.11 Pipeline Register Optimization
[21:30:59] Phase 4 Post Placement Optimization and Clean-Up
[21:30:59] Phase 4.1 Post Commit Optimization
[21:30:59] Phase 4.1.1 Post Placement Optimization
[21:30:59] Phase 4.1.1.1 BUFG Insertion
[21:30:59] Phase 4.2 Post Placement Cleanup
[21:31:04] Phase 4.3 Placer Reporting
[21:31:04] Phase 4.4 Final Placement Cleanup
[21:31:09] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 01m 15s 

[21:31:09] Starting logic routing..
[21:31:24] Phase 1 Build RT Design
[21:32:05] Phase 2 Router Initialization
[21:32:05] Phase 2.1 Create Timer
[21:32:05] Phase 2.2 Fix Topology Constraints
[21:32:05] Phase 2.3 Pre Route Cleanup
[21:32:05] Phase 2.4 Global Clock Net Routing
[21:32:10] Phase 2.5 Update Timing
[21:32:10] Phase 3 Initial Routing
[21:32:15] Phase 4 Rip-up And Reroute
[21:32:15] Phase 4.1 Global Iteration 0
[21:32:20] Phase 4.2 Additional Iteration for Hold
[21:32:20] Phase 5 Delay and Skew Optimization
[21:32:20] Phase 5.1 Delay CleanUp
[21:32:20] Phase 5.1.1 Update Timing
[21:32:20] Phase 5.2 Clock Skew Optimization
[21:32:20] Phase 6 Post Hold Fix
[21:32:20] Phase 6.1 Hold Fix Iter
[21:32:20] Phase 6.1.1 Update Timing
[21:32:20] Phase 7 Route finalize
[21:32:20] Phase 8 Verifying routed nets
[21:32:20] Phase 9 Depositing Routes
[21:32:20] Phase 10 Post Router Timing
[21:32:25] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 01m 16s 

[21:32:25] Starting bitstream generation..
[21:33:46] Creating bitmap...
[21:33:51] Writing bitstream ./ultra96_wrapper.bit...
[21:33:51] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 01m 26s 

INFO: [VPL 60-841] Created output file: /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/p0/vpl/_new_clk_freq
INFO: [VPL 60-841] Created output file: /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/p0/vpl/system.bit
INFO: [VPL 60-841] Created output file: /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/p0/vpl/system.hdf
INFO: [VPL 60-841] Created output file: /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/p0/vpl/address_map.xml
Software tracing enabled
Compile hardware access API functions
Create board support package library
Link application ELF file
SD card folder created /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/sd_card
All user specified timing constraints are met.
sds++ log file saved as /home/hidemi/workspace/Ultra96/sdsoc/sample/Debug/_sds/reports/sds.log

Finished building target: sample.elf

21:34:54 Build Finished (took 16m:42s.421ms)