Vitis AIの構造を勉強しなくてよくなった

Vitis AIを勉強し始めて約2週間になろうとしてた「Vitis AIの構造を勉強してみた」の12日目、事件が起きた。

ACRiにVitis AIがとてもわかりやすい記事が投下された。

Vitis を用いたアクセラレータの開発 (1) Vitisとは?

「マジでぇ〜!!!」

ACRiの記事はすごくわかりやすくて、これこそが知りたかった結果なのだ。

しかし、それは遅かった。

今日のブログの草案を書き上げたところでACRiの記事が降ってきたのだ。

それは、今日、ガッツリと調べてたどり着いたところだった。

今日の前置きはACRiの記事を見たあとに書き足したものである。

そして、「Vitis AIの構造を勉強してみた」の最終日なのである。

せっかく、ガッツリやってみたので備忘録程度に記録する。

ガッツリやってみるか…

ぼちぼちと調べるのも飽きてきたのでガッツリやってみるか。

2週間近くになろうとしているが、いまいち、全体像が掴めない。

上から攻めるのではなく、中腹から攻めてみよう。

XRTにアクセスする部分があるはずだからそこから探してみる。

(このブログは長くなってしまったけど、ACRiの記事を見る前に書き残していたものなので右往左往している様がよくわかる)

XRTをどこからアクセスするか探る

XRTにアクセスする部分はおそらく、XRT関係のヘッダファイルを読み込んでいるだろうと予測して、次のように探してみる。

grep -R -i xrt | grep -i include

ファイルはたくさんひっかかったが、そのうちでも次のディレクトリのソースコードが今調べているfacedetectでXRTにアクセスする候補っぽい。

tools/Vitis-AI-Library/usefultools/src
tools/Vitis-AI-Runtime/VART/vart/xrt-device-handle/src
tools/Vitis-AI-Runtime/VART/vart/xrnn-runner/src
tools/Vitis-AI-Runtime/VART/vart/dpu-controller/src
tools/Vitis-AI-Quantizer/vai_q_tensorflow1.x/tensorflow/compiler
dsa/DPU-TRD/app/samples/include/xir

これらのディレクトリにあるソースコードを見たけど、それらしいところはなかった。

もしかして、xclOpen関数で見つかるかと検索してみたが、それらしいところがなかった。

いろいろ、探し回ったけどどこがハードウェアの入り口になっているかわからなかった。

もう、諦めたほうが良いのかもしれない。

とりあえず、スタートに戻ってVitis AIを構成するVitis環境から確認しよう。

(この時点ではACRiの記事に気がついていない)

XSAファイルを確認

XSAファイルは次のファイルしか存在しない。

Vitis-AI/dsa/DPU-TRD/prj/Vivado/pre-built/top_wrapper.xsa

XSAファイルはVitis向けのPlatformファイルでただのZIP圧縮がかかっているだけである。

$ unzip -l top_wrapper.xsa
Archive:  top_wrapper.xsa
E4uF2MSOouwZDMlSbZQy7Wj44ImQBrmge9kZSX3koFmqM=
  Length      Date    Time    Name
---------  ---------- -----   ----
 18311290  2020-11-04 18:54   top_wrapper.bit
     1126  2020-11-04 18:54   sysdef.xml
   643545  2020-11-04 18:54   top.hwh
    34710  2020-11-04 18:54   top.bda
   938741  2020-11-04 18:54   psu_init.c
  1612083  2020-11-04 18:54   psu_init.h
   939123  2020-11-04 18:54   psu_init_gpl.c
  1612687  2020-11-04 18:54   psu_init_gpl.h
    52624  2020-11-04 18:54   psu_init.html
   849804  2020-11-04 18:54   psu_init.tcl
     1079  2020-11-04 18:54   xsa.xml
     2102  2020-11-04 18:54   xsa.json
---------                     -------
 24998914                     12 files

さっそく、展開してファイルを確認する。

まずはxsa.xmlから確認しよう。

<?xml version="1.0" encoding="UTF-8"?>
<Root VersionMajor="1" VersionMinor="15">
  <GenAppInfo Name="Vivado" Version="2020.2" CL="3051627" TimeStamp="Wed Nov  4 18:54:47 2020"/>
  <DSA Vendor="xilinx" BoardId="" Name="" VersionMajor="0" VersionMinor="0" Description="Vivado generated Hardware Platform" FeatureRomTimestamp="0" DcpLogicFunctionStripped="false" DcpEncrypt="false" Unified="true" Fixed="true" DefaultOutputType="hw_export">
    <Build UsesPR="false" PlatformState="pre_synth" AcceleratorBinaryContent="bitstream" ValidBinaryContentValues="dcp,bitstream" TopModuleName="top_wrapper"/>
    <Board Name="" Vendor="" Part="">
      <Images>
        <Img Type="HDPI" File=""/>
        <Img Type="MDPI" File=""/>
        <Img Type="LDPI" File=""/>
      </Images>
    </Board>
    <Devices>
      <Device Name="fpga0" Type="8" FpgaDevice="zynquplus:xczu9eg:ffvb1156:-2:i">
        <Core Name="OCL_REGION_0" Type="clc_region" ComputeUnits="60"/>
      </Device>
    </Devices>
    <Files>
      <File Type="FULL_BIT" Name="top_wrapper.bit"/>
    </Files>
  </DSA>
</Root>

DeviceがFpgaDevice="zynquplus:xczu9eg:ffvb1156:-2:i"である。

ZCU102はXCZU9EG-2FFVB1156、ZCU104はXCZU7EV-2FFVC1156なのでZCU102のXSAファイルだとわかる。

ZCU104用のリファレンスモデルは存在しないことがわかった。

Vitis-AI/dsa/DPU-TRD/prj/Vitisのディレクトリが気になるので明日にしよう。

じゃぁ、Vitis-AI/dsa/DPU-TRD/prj/Vitisをしらべてみようかしら。

ZCU104向けVivado環境がないのはわかったけど、Vitis環境がないか探ってみる。

ZCU104のVitis環境は作成できるか?

ディレクトリの移動と環境設定をする。

$ cd ./Vitis-AI/dsa/DPU-TRD/prj/Vitis
$ source /opt/Xilinx/Vitis/2020.2/settings64.sh 

なになに、README.mdに次のようなことが書いている。

steps:

1.Modify the Makefile file, Update the $XOCC_OPTS parameters
--config ${TRD_HOME}/prj/Vitis/config_file/prj_config_104_2dpu

2.Enable the URAM and modify the RAM USAGE
Need to modify the dpu_conf.vh file
line37: `define URAM_ENABLE

3.
% make KERNEL=DPU DEVICE=zcu104

さっそく、Makefileを変更してみる。

Makefileを変更したらmakeすればいいのね。

$ make KERNEL=DPU DEVICE=zcu104
/opt/Xilinx/Vivado/2020.2/bin/vivado -mode batch -source scripts/gen_dpu_xo.tcl -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu104

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source scripts/gen_dpu_xo.tcl
# if { $::argc != 4 } {
#     puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
#     puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n"
#     exit
# }
# set xoname    [lindex $::argv 0]
# set krnl_name [lindex $::argv 1]
# set target    [lindex $::argv 2]
# set device    [lindex $::argv 3]
# puts $xoname
binary_container_1/dpu.xo
# set suffix "${krnl_name}_${target}_${device}"
# source -notrace ./scripts/package_dpu_kernel.tcl
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_impl_clocks_xdc.ttcl'
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_clocks_xdc.ttcl'
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'FREQ_HZ' with value '300000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'FREQ_HZ' with value '600000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-7067] Note that bus interface 'aclk' has a fixed FREQ_HZ of '300000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-7067] Note that bus interface 'ap_clk_2' has a fixed FREQ_HZ of '600000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
# if {[file exists "${xoname}"]} {
#     file delete -force "${xoname}"
# }
# package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory ./packaged_kernel_${suffix} -kernel_xml ./kernel_xml/dpu/kernel.xml
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Sun Jan 10 22:23:33 2021...
v++ -t hw --platform  --save-temps --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

ERROR: [v++ 60-1258] No valid platform was found that matches '--save-temps'. Please make sure that the platform is specified correctly, and the platform has the right version number. The platform repo paths are:
    /opt/Xilinx/Vitis/2020.2/platforms
The valid platforms found from the above repo paths are:

ERROR: [v++ 60-587] Failed to add a platform: specified platform --save-temps is not found or is not valid
INFO: [v++ 60-1662] Stopping dispatch session having empty uuid.
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:70: binary_container_1/dpu.xclbin] エラー 1

makeコマンドが走ったので「ヤッター!」と思ったけどエラー終了した。

エラーで示しているディレクトリって(/opt/Xilinx/Vitis/2020.2/platforms)何があるの?

$ ls /opt/Xilinx/Vitis/2020.2/platforms
achromatic  blanche  platform_keys_doc.json

ファイルが3つだけあった。

$ sudo chmod 777 /opt/Xilinx/Vitis/2020.2/platforms

V++の引数は次のWebページに載っている。

https://www.xilinx.com/html_docs/xilinx2020_2/vitis_doc/vitiscommandcompiler.html

--save_tempは中間ファイルを置くディレクトリを示す引数であることが分かった。

そこで--save_temp ./tempとしてmakeした。

$ make KERNEL=DPU DEVICE=zcu104
/opt/Xilinx/Vivado/2020.2/bin/vivado -mode batch -source scripts/gen_dpu_xo.tcl -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu104

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source scripts/gen_dpu_xo.tcl
# if { $::argc != 4 } {
#     puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
#     puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n"
#     exit
# }
# set xoname    [lindex $::argv 0]
# set krnl_name [lindex $::argv 1]
# set target    [lindex $::argv 2]
# set device    [lindex $::argv 3]
# puts $xoname
binary_container_1/dpu.xo
# set suffix "${krnl_name}_${target}_${device}"
# source -notrace ./scripts/package_dpu_kernel.tcl
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_impl_clocks_xdc.ttcl'
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_clocks_xdc.ttcl'
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'FREQ_HZ' with value '300000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'FREQ_HZ' with value '600000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-7067] Note that bus interface 'aclk' has a fixed FREQ_HZ of '300000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-7067] Note that bus interface 'ap_clk_2' has a fixed FREQ_HZ of '600000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
# if {[file exists "${xoname}"]} {
#     file delete -force "${xoname}"
# }
# package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory ./packaged_kernel_${suffix} -kernel_xml ./kernel_xml/dpu/kernel.xml
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Sun Jan 10 22:38:31 2021...
v++ -t hw --platform  --save-temps ./temp --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

ERROR: [v++ 60-602] Source file does not exist: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/temp
INFO: [v++ 60-1662] Stopping dispatch session having empty uuid.
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:70: binary_container_1/dpu.xclbin] エラー 1

tempがないとエラーしたのでmkdir tempでディレクトリを追加してmakeしてみた。

$ make KERNEL=DPU DEVICE=zcu104
/opt/Xilinx/Vivado/2020.2/bin/vivado -mode batch -source scripts/gen_dpu_xo.tcl -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu104

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source scripts/gen_dpu_xo.tcl
# if { $::argc != 4 } {
#     puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
#     puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n"
#     exit
# }
# set xoname    [lindex $::argv 0]
# set krnl_name [lindex $::argv 1]
# set target    [lindex $::argv 2]
# set device    [lindex $::argv 3]
# puts $xoname
binary_container_1/dpu.xo
# set suffix "${krnl_name}_${target}_${device}"
# source -notrace ./scripts/package_dpu_kernel.tcl
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_impl_clocks_xdc.ttcl'
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_clocks_xdc.ttcl'
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'FREQ_HZ' with value '300000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'FREQ_HZ' with value '600000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-7067] Note that bus interface 'aclk' has a fixed FREQ_HZ of '300000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-7067] Note that bus interface 'ap_clk_2' has a fixed FREQ_HZ of '600000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
# if {[file exists "${xoname}"]} {
#     file delete -force "${xoname}"
# }
# package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory ./packaged_kernel_${suffix} -kernel_xml ./kernel_xml/dpu/kernel.xml
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Sun Jan 10 22:38:31 2021...
v++ -t hw --platform  --save-temps ./temp --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

ERROR: [v++ 60-602] Source file does not exist: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/temp
INFO: [v++ 60-1662] Stopping dispatch session having empty uuid.
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:70: binary_container_1/dpu.xclbin] エラー 1
$ mkdir temp
$ make KERNEL=DPU DEVICE=zcu104
v++ -t hw --platform  --save-temps ./temp --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_link.ini'.
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

ERROR: [v++ 60-603] Source file is a directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/temp
INFO: [v++ 60-1662] Stopping dispatch session having empty uuid.
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:70: binary_container_1/dpu.xclbin] エラー 1

tempはディレクトリというエラーがでた。

ちょっと待ってよ。

じゃぁ、何のえらーなんだよ、何を指定すればいいの?

苦し紛れにディレクトリをやめてtouch tempとかしてみる?

$ make KERNEL=DPU DEVICE=zcu104
/opt/Xilinx/Vivado/2020.2/bin/vivado -mode batch -source scripts/gen_dpu_xo.tcl -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu104

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source scripts/gen_dpu_xo.tcl
# if { $::argc != 4 } {
#     puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
#     puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n"
#     exit
# }
# set xoname    [lindex $::argv 0]
# set krnl_name [lindex $::argv 1]
# set target    [lindex $::argv 2]
# set device    [lindex $::argv 3]
# puts $xoname
binary_container_1/dpu.xo
# set suffix "${krnl_name}_${target}_${device}"
# source -notrace ./scripts/package_dpu_kernel.tcl
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_impl_clocks_xdc.ttcl'
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_clocks_xdc.ttcl'
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'FREQ_HZ' with value '300000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'FREQ_HZ' with value '600000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-7067] Note that bus interface 'aclk' has a fixed FREQ_HZ of '300000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-7067] Note that bus interface 'ap_clk_2' has a fixed FREQ_HZ of '600000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
# if {[file exists "${xoname}"]} {
#     file delete -force "${xoname}"
# }
# package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory ./packaged_kernel_${suffix} -kernel_xml ./kernel_xml/dpu/kernel.xml
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Sun Jan 10 22:45:29 2021...
v++ -t hw --platform  --save-temps ./temp --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

ERROR: [v++ 60-630] Only the XO or O input file types are allowed for link flow.
INFO: [v++ 60-1662] Stopping dispatch session having empty uuid.
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:70: binary_container_1/dpu.xclbin] エラー 1

まぁ、マシなエラーになったけど、XOファイルOファイルでなきゃいけないってどういうこと?

ホントに?

$ tree
.
├── Makefile
├── README.md
├── binary_container_1
│   ├── dpu.xo
│   └── logs
│       └── v++_dpu.log
├── config_file
│   ├── prj_config
│   ├── prj_config_102_3dpu
│   ├── prj_config_102_3dpu_LPD
│   ├── prj_config_104_2dpu
│   ├── prj_config_1dpu
│   └── prj_config_gui
├── doc
│   ├── 5.3.3.png
│   ├── 6.1.png
│   ├── 6.10.png
│   ├── 6.11.png
│   ├── 6.12.png
│   ├── 6.13.png
│   ├── 6.14.png
│   ├── 6.15.png
│   ├── 6.2.png
│   ├── 6.4.png
│   ├── 6.5.png
│   ├── 6.6.png
│   ├── 6.7.png
│   ├── 6.8.png
│   ├── 6.9.png
│   ├── URL.png
│   ├── app.png
│   ├── download.png
│   ├── dpu_hardware_arch.png
│   ├── ide.png
│   ├── install.png
│   ├── prj_conf.png
│   ├── softmax.png
│   └── sysroot.png
├── dpu_conf.vh
├── kernel_xml
│   ├── dpu
│   │   └── kernel.xml
│   └── sfm
│       └── kernel.xml
├── packaged_kernel_DPUCZDX8G_hw_zcu104
│   ├── component.xml
│   ├── src
│   │   ├── DPUCZDX8G.v
│   │   ├── DPUCZDX8G_v3_3_0_vl_dpu.sv
│   │   ├── arch_def.vh
│   │   ├── arch_para.vh
│   │   ├── dpu_conf.vh
│   │   ├── fingerprint_json.ttcl
│   │   ├── function.vh
│   │   └── timing_clocks.xdc
│   └── xgui
│       └── DPUCZDX8G_v1_0.tcl
├── sample_link.ini
├── scripts
│   ├── gen_dpu_xo.tcl
│   ├── gen_sfm_xo.tcl
│   ├── package_dpu_kernel.tcl
│   └── package_sfm_kernel.tcl
├── scripts_gui
│   ├── gen_dpu_xo.tcl
│   ├── gen_sfm_xo.tcl
│   ├── package_dpu_kernel.tcl
│   └── package_sfm_kernel.tcl
├── syslink
│   ├── strip_interconnects.tcl
│   ├── zcu102_lowpower.tcl
│   └── zcu104_lowpower.tcl
├── temp
├── tmp_kernel_pack_DPUCZDX8G_hw_zcu104
│   ├── kernel_pack.cache
│   │   └── wt
│   │       └── project.wpc
│   ├── kernel_pack.hw
│   │   └── kernel_pack.lpr
│   ├── kernel_pack.ip_user_files
│   └── kernel_pack.xpr
├── vivado.jou
└── vivado.log

いちおう、binary_container_1/dpu.xoにあるんだけど、これじゃぁダメなの?

なんか違ってたようだ。

README.mdがあるやん!!!

README.mdをよく読めって感じだな。

もう一回、仕切り直しだ。

README.mdを読んでVitis環境を作ってみる

次のURLからZYNQMP common imageとZCU104 Base 2020.2をダウンロードする。

https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/embedded-platforms.html

$ cd ./Vitis-AI/dsa/DPU-TRD/prj/Vitis
$ source /opt/Xilinx/Vitis/2020.2/settings64.sh
$ tar xvf xilinx-zynqmp-common-v2020.2.tar.gz
$ unzip xilinx_zcu104_base_202020_1.zip
$ export EDGE_COMMON_SW=./xilinx-zynqmp-common-v2020.2 
$ export SDX_PLATFORM=./xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm
$ make KERNEL=DPU DEVICE=zcu104

さて、ビルドできるかな?

$ make KERNEL=DPU DEVICE=zcu104
/opt/Xilinx/Vivado/2020.2/bin/vivado -mode batch -source scripts/gen_dpu_xo.tcl -tclargs binary_container_1/dpu.xo DPUCZDX8G hw zcu104

****** Vivado v2020.2 (64-bit)
  **** SW Build 3064766 on Wed Nov 18 09:12:47 MST 2020
  **** IP Build 3064653 on Wed Nov 18 14:17:31 MST 2020
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

source scripts/gen_dpu_xo.tcl
# if { $::argc != 4 } {
#     puts "ERROR: Program \"$::argv0\" requires 4 arguments!\n"
#     puts "Usage: $::argv0 <xoname> <krnl_name> <target> <device>\n"
#     exit
# }
# set xoname    [lindex $::argv 0]
# set krnl_name [lindex $::argv 1]
# set target    [lindex $::argv 2]
# set device    [lindex $::argv 3]
# puts $xoname
binary_container_1/dpu.xo
# set suffix "${krnl_name}_${target}_${device}"
# source -notrace ./scripts/package_dpu_kernel.tcl
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_impl_clocks_xdc.ttcl'
WARNING: [Vivado 12-818] No files matched '../../dpu_ip/DPUCZDX8G_v3_3_0/ttcl/timing_clocks_xdc.ttcl'
INFO: [IP_Flow 19-5654] Module 'DPUCZDX8G' uses SystemVerilog sources with a Verilog top file. These SystemVerilog files will not be analysed by the packager.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "src/arch_def.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1842] HDL Parser: Found include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" from the top-level HDL file.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagesynthesis.
INFO: [IP_Flow 19-1841] HDL Parser: Add include file "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" to file group xilinx_anylanguagebehavioralsimulation.
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aclk' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from X_INTERFACE_INFO parameter from HDL file).
INFO: [IP_Flow 19-5107] Inferred bus interface 'aresetn' of definition 'xilinx.com:signal:reset:1.0' (from 'X_INTERFACE_INFO' attribute).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_GP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP0' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'M_AXI_HP2' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'S_AXI_CONTROL' of definition 'xilinx.com:interface:aximm:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-5107] Inferred bus interface 'interrupt' of definition 'xilinx.com:signal:interrupt:1.0' (from Xilinx Repository).
INFO: [IP_Flow 19-4728] Bus Interface 'interrupt': Added interface parameter 'SENSITIVITY' with value 'LEVEL_HIGH'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_BUSIF' with value 'M_AXI_GP0'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'ASSOCIATED_RESET' with value 'aresetn'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'ASSOCIATED_RESET' with value 'ap_rst_n_2'.
INFO: [IP_Flow 19-4728] Bus Interface 'aclk': Added interface parameter 'FREQ_HZ' with value '300000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_clk_2': Added interface parameter 'FREQ_HZ' with value '600000000'.
INFO: [IP_Flow 19-4728] Bus Interface 'ap_rst_n_2': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-4728] Bus Interface 'aresetn': Added interface parameter 'POLARITY' with value 'ACTIVE_LOW'.
INFO: [IP_Flow 19-7067] Note that bus interface 'aclk' has a fixed FREQ_HZ of '300000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
INFO: [IP_Flow 19-7067] Note that bus interface 'ap_clk_2' has a fixed FREQ_HZ of '600000000'. This value will be respected whenever this IP is instantiated in IP Integrator.
WARNING: [IP_Flow 19-5661] Bus Interface 'ap_clk_2' does not have any bus interfaces associated with it.
WARNING: [IP_Flow 19-3157] Bus Interface 'ap_rst_n_2': Bus parameter POLARITY is ACTIVE_LOW but port 'ap_rst_n_2' is not *resetn - please double check the POLARITY setting.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagesynthesis (Synthesis)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Synthesis file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Synthesis'.
Resolution: Remove the file from the specified file group.
WARNING: [IP_Flow 19-731] File Group 'xilinx_anylanguagebehavioralsimulation (Simulation)': "/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh" file path is not relative to the IP root directory.
WARNING: [IP_Flow 19-4816] The Simulation file group has two include files that have the same base name. It is not guaranteed which of these two files will be picked up during synthesis/simulation:   src/dpu_conf.vh
  /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu_conf.vh
WARNING: [IP_Flow 19-991] Unrecognized or unsupported file 'src/fingerprint_json.ttcl' found in file group 'Simulation'.
Resolution: Remove the file from the specified file group.
INFO: [IP_Flow 19-2181] Payment Required is not set for this core.
INFO: [IP_Flow 19-2187] The Product Guide file is missing.
ipx::package_project: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 2433.008 ; gain = 0.344 ; free physical = 38169 ; free virtual = 58589
INFO: [IP_Flow 19-795] Syncing license key meta-data
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository '/opt/Xilinx/Vivado/2020.2/data/ip'.
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_clk_2' of definition 'xilinx.com:signal:clock:1.0' (from TCL Argument).
INFO: [IP_Flow 19-5107] Inferred bus interface 'ap_rst_n_2' of definition 'xilinx.com:signal:reset:1.0' (from TCL Argument).
# if {[file exists "${xoname}"]} {
#     file delete -force "${xoname}"
# }
# package_xo -xo_path ${xoname} -kernel_name ${krnl_name} -ip_directory ./packaged_kernel_${suffix} -kernel_xml ./kernel_xml/dpu/kernel.xml
WARNING: [Vivado 12-4404] The CPU emulation flow in v++ is only supported when using a packaged XO file that contains C-model files, none were found.
INFO: [Common 17-206] Exiting Vivado at Sun Jan 10 23:31:17 2021...
v++ -t hw --platform ./xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm --save-temps --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 82-185] Check out the auto-generated 'sample_link.ini' configuration file. The file shows how to migrate from deprecated command line --xp switches to configuration file directives.
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
    Reports: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link
    Log files: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link
Running Dispatch Server on port:34823
INFO: [v++ 60-1548] Creating build summary session with primary output /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin.link_summary, at Sun Jan 10 23:31:31 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Sun Jan 10 23:31:31 2021
Running Rule Check Server on port:45341
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link/v++_link_dpu_guidance.html', at Sun Jan 10 23:31:32 2021
INFO: [v++ 60-895]   Target platform: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/hw/xilinx_zcu104_base_202020_1.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: xilinx_zcu104_base_202020_1
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [23:31:33] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xo -keep --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/syslinkConfig.ini --xpfm /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm --target hw --output_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int --temp_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Sun Jan 10 23:31:34 2021
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [23:31:34] build_xd_ip_db started: /opt/Xilinx/Vitis/2020.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/xilinx_zcu104_base_202020_1.hpfm -clkid 0 -ip /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/iprepo/xilinx_com_RTLKernel_DPUCZDX8G_1_0,DPUCZDX8G -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [23:31:37] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1621.238 ; gain = 316.383 ; free physical = 37954 ; free virtual = 58884
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [23:31:37] cfgen started: /opt/Xilinx/Vitis/2020.2/bin/cfgen  -nk DPUCZDX8G:2 -sp DPUCZDX8G_1.M_AXI_GP0:HPC0 -sp DPUCZDX8G_1.M_AXI_HP0:HP0 -sp DPUCZDX8G_1.M_AXI_HP2:HP1 -sp DPUCZDX8G_2.M_AXI_GP0:HPC0 -sp DPUCZDX8G_2.M_AXI_HP0:HP2 -sp DPUCZDX8G_2.M_AXI_HP2:HP3 -clock.id 1:DPUCZDX8G_1.aclk -clock.id 6:DPUCZDX8G_1.ap_clk_2 -clock.id 1:DPUCZDX8G_2.aclk -clock.id 6:DPUCZDX8G_2.ap_clk_2 -dmclkid 0 -r /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G, num: 2  {DPUCZDX8G_1 DPUCZDX8G_2}
INFO: [CFGEN 83-0] Port Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP0, sptag: HP0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP2, sptag: HP1
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP0, sptag: HP2
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP2, sptag: HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_instr_addr to HPC0 for directive DPUCZDX8G_1.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_prof_addr to HPC0 for directive DPUCZDX8G_1.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base0_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base1_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base2_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base3_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base4_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base5_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base6_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base7_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_instr_addr to HPC0 for directive DPUCZDX8G_2.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_prof_addr to HPC0 for directive DPUCZDX8G_2.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base0_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base1_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base2_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base3_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base4_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base5_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base6_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base7_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [SYSTEM_LINK 82-37] [23:31:39] cfgen finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1621.238 ; gain = 0.000 ; free physical = 37900 ; free virtual = 58880
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [23:31:39] cf2bd started: /opt/Xilinx/Vitis/2020.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd --temp_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link --output_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [23:31:41] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1621.238 ; gain = 0.000 ; free physical = 37814 ; free virtual = 58869
INFO: [v++ 60-1441] [23:31:41] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 37852 ; free virtual = 58907
INFO: [v++ 60-1443] [23:31:41] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/sdsl.dat -rtd /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/cf2sw.rtd -nofilter /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/cf2sw_full.rtd -xclbin /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [23:31:43] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 37812 ; free virtual = 58914
INFO: [v++ 60-1443] [23:31:43] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [23:31:44] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.82 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 37564 ; free virtual = 58684
INFO: [v++ 60-1443] [23:31:44] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm --remote_ip_cache /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/ip_cache -s --output_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int --log_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link --report_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/vplConfig.ini -k /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link --no-info --iprepo /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_DPUCZDX8G_1_0 --messageDb /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link/vpl.pb /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link

****** vpl v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: xilinx_zcu104_base_202020_1
INFO: [VPL 60-1032] Extracting hardware platform to /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/.local/hw_platform
WARNING: /opt/Xilinx/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.
[23:31:52] Run vpl: Step create_project: Started
Creating Vivado project.
[23:31:56] Run vpl: Step create_project: Completed
[23:31:56] Run vpl: Step create_bd: Started
[23:32:04] Run vpl: Step create_bd: Completed
[23:32:04] Run vpl: Step update_bd: Started
[23:32:04] Run vpl: Step update_bd: Completed
[23:32:04] Run vpl: Step generate_target: Started
[23:32:32] Run vpl: Step generate_target: Completed
[23:32:32] Run vpl: Step config_hw_runs: Started
[23:32:33] Run vpl: Step config_hw_runs: Completed
[23:32:33] Run vpl: Step synth: Started
[23:33:04] Block-level synthesis in progress, 0 of 15 jobs complete, 8 jobs running.
[23:33:34] Block-level synthesis in progress, 3 of 15 jobs complete, 5 jobs running.
[23:34:04] Block-level synthesis in progress, 11 of 15 jobs complete, 3 jobs running.
[23:34:34] Block-level synthesis in progress, 12 of 15 jobs complete, 2 jobs running.
[23:35:04] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:35:34] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:36:04] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:36:34] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:37:04] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:37:34] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:38:04] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:38:35] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:39:05] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:39:35] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:40:05] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:40:35] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:41:05] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:41:35] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:42:05] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:42:35] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:43:05] Block-level synthesis in progress, 13 of 15 jobs complete, 1 job running.
[23:43:35] Block-level synthesis in progress, 14 of 15 jobs complete, 0 jobs running.
[23:44:05] Top-level synthesis in progress.
[23:44:38] Run vpl: Step synth: Completed
[23:44:38] Run vpl: Step impl: Started
[23:47:40] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 15m 54s 

[23:47:40] Starting logic optimization..
[23:47:40] Phase 1 Retarget
[23:47:40] Phase 2 Constant propagation
[23:48:10] Phase 3 BUFG optimization
[23:48:10] Phase 4 Shift Register Optimization
[23:48:10] Phase 5 Sweep
[23:48:10] Phase 6 Constant propagation
[23:48:10] Phase 7 Sweep
[23:48:10] Phase 8 Remap
[23:48:40] Phase 9 Post Processing Netlist
[23:49:10] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 01m 30s 

[23:49:10] Starting logic placement..
[23:49:10] Phase 1 Placer Initialization
[23:49:10] Phase 1.1 Placer Initialization Netlist Sorting
[23:49:10] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[23:49:40] Phase 1.3 Build Placer Netlist Model
[23:50:10] Phase 1.4 Constrain Clocks/Macros
[23:50:10] Phase 2 Global Placement
[23:50:10] Phase 2.1 Floorplanning
[23:50:10] Phase 2.1.1 Partition Driven Placement
[23:50:10] Phase 2.1.1.1 PBP: Partition Driven Placement
[23:51:40] Phase 2.1.1.2 PBP: Clock Region Placement
[23:51:40] Phase 2.1.1.3 PBP: Discrete Incremental
[23:51:40] Phase 2.1.1.4 PBP: Compute Congestion
[23:51:40] Phase 2.1.1.5 PBP: Macro Placement
[23:52:10] Phase 2.1.1.6 PBP: UpdateTiming
[23:52:10] Phase 2.1.1.7 PBP: Add part constraints
[23:52:10] Phase 2.2 Update Timing before SLR Path Opt
[23:52:10] Phase 2.3 Global Placement Core
[23:54:41] Phase 2.3.1 Physical Synthesis In Placer
[23:56:11] Phase 3 Detail Placement
[23:56:11] Phase 3.1 Commit Multi Column Macros
[23:56:11] Phase 3.2 Commit Most Macros & LUTRAMs
[23:57:11] Phase 3.3 Small Shape DP
[23:57:11] Phase 3.3.1 Small Shape Clustering
[23:57:11] Phase 3.3.2 Flow Legalize Slice Clusters
[23:57:11] Phase 3.3.3 Slice Area Swap
[23:58:12] Phase 3.4 Re-assign LUT pins
[23:58:12] Phase 3.5 Pipeline Register Optimization
[23:58:12] Phase 3.6 Fast Optimization
[23:58:42] Phase 4 Post Placement Optimization and Clean-Up
[23:58:42] Phase 4.1 Post Commit Optimization
[23:58:47] Run vpl: Step impl: Failed
[23:58:47] Run vpl: FINISHED. Run Status: impl ERROR
ERROR: [VPL 60-773] In '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/vivado.log', caught Tcl error:  problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-777] Sorry, but it appears that a Xilinx program has terminated unexpectedly. Please contact Xilinx technical support for further assistance and give them the contents of the CrashLog directory in /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [23:58:47] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:06 ; elapsed = 00:27:03 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 36107 ; free virtual = 57885
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:70: binary_container_1/dpu.xclbin] エラー 1

ダメや〜ん!!!

まぁ、でもいい線いったんじゃない?

エラー内容を探る

/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.logを覗いてエラーを確認する。

Phase 4.1 Post Commit Optimization
INFO: [Timing 38-35] Done setting XDC timing constraints.
/opt/Xilinx/Vivado/2020.2/bin/rdiArgs.sh: 309 行: 178951 Segmentation fault      "$RDI_PROG" "$@"
segfault in /opt/Xilinx/Vivado/2020.2/bin/unwrapped/lnx64.o/vivado -exec vivado -log xilinx_zcu104_base_wrapper.vdi -applog -m64 -product Vivado -messageDb vivado.pb -mode batch -source xilinx_zcu104_base_wrapper.tcl -notrace, exiting...

なんと、Segmentation faultでした。

それ、積んでねぇ?

$ cd ./Vitis-AI/dsa/DPU-TRD/prj/Vitis
$ source /opt/Xilinx/Vitis/2020.2/settings64.sh
$ vivado &

GUIで見てみる

ちょっと、Vivadoで覗いてみよう。

XPRファイルを探してみます。

$ find ./|grep "\.xpr$"
./tmp_kernel_pack_DPUCZDX8G_hw_zcu104/kernel_pack.xpr
./binary_container_1/link/vivado/vpl/prj/prj.xpr

2つありましたが、下っぽいですね。

開いてみましょう。

あぁ、これっぽい。

Segmentation faultだったので、GUIの状態で一度、プロジェクトをクリーンナップしてから合成してみよう。

そしたら、VivadoであればBitStreamができた。

なんでやねん。

ザ・リトライ

もう一度、コマンドラインでビルドしてみよう。

これでまたSegmentation faultだったらどうしようかしら?

$ make clean
$ make KERNEL=DPU DEVICE=zcu104
中略
[23:58:42] Phase 4.1 Post Commit Optimization
[23:58:47] Run vpl: Step impl: Failed
[23:58:47] Run vpl: FINISHED. Run Status: impl ERROR
ERROR: [VPL 60-773] In '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/vivado.log', caught Tcl error:  problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-777] Sorry, but it appears that a Xilinx program has terminated unexpectedly. Please contact Xilinx technical support for further assistance and give them the contents of the CrashLog directory in /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link
WARNING: [VPL 60-732] Link warning: No monitor points found for BD automation.
ERROR: [VPL 60-704] Integration error, problem implementing dynamic region, impl_1: place_design ERROR, please look at the run log file '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/prj/prj.runs/impl_1/runme.log' for more information
ERROR: [VPL 60-1328] Vpl run 'vpl' failed
ERROR: [VPL 60-806] Failed to finish platform linker
INFO: [v++ 60-1442] [23:58:47] Run run_link: Step vpl: Failed
Time (s): cpu = 00:00:06 ; elapsed = 00:27:03 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 36107 ; free virtual = 57885
ERROR: [v++ 60-661] v++ link run 'run_link' failed
ERROR: [v++ 60-626] Kernel link failed to complete
ERROR: [v++ 60-703] Failed to finish linking
INFO: [v++ 60-1653] Closing dispatch client.
make: *** [Makefile:70: binary_container_1/dpu.xclbin] エラー 1

結果はやはりSegmentation faultだった。

だからぁ〜、なんでSegmentation faultなの?

やっぱり、積んでる?

レッツ!リトライ!!!

そういえば、「Xilinxのビルドって2度目のmakeで通ることってあるよね」理論を適用してmake cleanをしないでもう一度、ビルドする。

Xilinx場合、こういう根拠ないことがまかり通ったりするんだよなぁ〜。

$ make KERNEL=DPU DEVICE=zcu104
v++ -t hw --platform ./xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm --save-temps --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/config_file/prj_config_104_2dpu --xp param:compiler.userPostSysLinkOverlayTcl=/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/syslink/strip_interconnects.tcl  -l --temp_dir binary_container_1 --log_dir binary_container_1/logs --remote_ip_cache binary_container_1/ip_cache -o "binary_container_1/dpu.xclbin" binary_container_1/dpu.xo
WARNING: [v++ 60-1600] The option 'xp' was used directly on the command line, where its usage is deprecated. To ensure input line works for supported operating systems or shells, v++ supports specification for some options in a configuration file. As an alternative, please use options 'advanced.*', 'vivado.*' in a configuration file. Use one or more configuration files along with section headers to define key-value pairs for the advanced properties or parameters. Specify a configuration file using '--config'.
INFO: [v++ 84-14] Sample config file already exists. To regenerate, remove file 'sample_link.ini'.
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ link can be found at:
    Reports: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link
    Log files: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link
Running Dispatch Server on port:45815
INFO: [v++ 60-1548] Creating build summary session with primary output /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin.link_summary, at Mon Jan 11 22:06:09 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Mon Jan 11 22:06:09 2021
Running Rule Check Server on port:33021
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link/v++_link_dpu_guidance.html', at Mon Jan 11 22:06:10 2021
INFO: [v++ 60-895]   Target platform: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/hw/xilinx_zcu104_base_202020_1.xsa'
INFO: [v++ 60-629] Linking for hardware target
INFO: [v++ 60-423]   Target device: xilinx_zcu104_base_202020_1
INFO: [v++ 60-1332] Run 'run_link' status: Not started
INFO: [v++ 60-1443] [22:06:10] Run run_link: Step system_link: Started
INFO: [v++ 60-1453] Command Line: system_link --xo /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xo -keep --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/syslinkConfig.ini --xpfm /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm --target hw --output_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int --temp_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [SYSTEM_LINK 60-1316] Initiating connection to rulecheck server, at Mon Jan 11 22:06:11 2021
INFO: [SYSTEM_LINK 82-70] Extracting xo v3 file /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xo
INFO: [SYSTEM_LINK 82-53] Creating IP database /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-38] [22:06:11] build_xd_ip_db started: /opt/Xilinx/Vitis/2020.2/bin/build_xd_ip_db -ip_search 0  -sds-pf /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/xilinx_zcu104_base_202020_1.hpfm -clkid 0 -ip /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/iprepo/xilinx_com_RTLKernel_DPUCZDX8G_1_0,DPUCZDX8G -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml
INFO: [SYSTEM_LINK 82-37] [22:06:14] build_xd_ip_db finished successfully
Time (s): cpu = 00:00:04 ; elapsed = 00:00:03 . Memory (MB): peak = 1621.238 ; gain = 316.383 ; free physical = 52174 ; free virtual = 63170
INFO: [SYSTEM_LINK 82-51] Create system connectivity graph
INFO: [SYSTEM_LINK 82-102] Applying explicit connections to the system connectivity graph: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [SYSTEM_LINK 82-38] [22:06:14] cfgen started: /opt/Xilinx/Vitis/2020.2/bin/cfgen  -nk DPUCZDX8G:2 -sp DPUCZDX8G_1.M_AXI_GP0:HPC0 -sp DPUCZDX8G_1.M_AXI_HP0:HP0 -sp DPUCZDX8G_1.M_AXI_HP2:HP1 -sp DPUCZDX8G_2.M_AXI_GP0:HPC0 -sp DPUCZDX8G_2.M_AXI_HP0:HP2 -sp DPUCZDX8G_2.M_AXI_HP2:HP3 -clock.id 1:DPUCZDX8G_1.aclk -clock.id 6:DPUCZDX8G_1.ap_clk_2 -clock.id 1:DPUCZDX8G_2.aclk -clock.id 6:DPUCZDX8G_2.ap_clk_2 -dmclkid 0 -r /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml
INFO: [CFGEN 83-0] Kernel Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G, num: 2  {DPUCZDX8G_1 DPUCZDX8G_2}
INFO: [CFGEN 83-0] Port Specs: 
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP0, sptag: HP0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_1, k_port: M_AXI_HP2, sptag: HP1
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_GP0, sptag: HPC0
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP0, sptag: HP2
INFO: [CFGEN 83-0]   kernel: DPUCZDX8G_2, k_port: M_AXI_HP2, sptag: HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_instr_addr to HPC0 for directive DPUCZDX8G_1.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_prof_addr to HPC0 for directive DPUCZDX8G_1.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base0_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base1_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base2_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base3_addr to HP0 for directive DPUCZDX8G_1.M_AXI_HP0:HP0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base4_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base5_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base6_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_1.dpu_base7_addr to HP1 for directive DPUCZDX8G_1.M_AXI_HP2:HP1
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_instr_addr to HPC0 for directive DPUCZDX8G_2.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_prof_addr to HPC0 for directive DPUCZDX8G_2.M_AXI_GP0:HPC0
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base0_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base1_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base2_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base3_addr to HP2 for directive DPUCZDX8G_2.M_AXI_HP0:HP2
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base4_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base5_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base6_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [CFGEN 83-2228] Creating mapping for argument DPUCZDX8G_2.dpu_base7_addr to HP3 for directive DPUCZDX8G_2.M_AXI_HP2:HP3
INFO: [SYSTEM_LINK 82-37] [22:06:16] cfgen finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1621.238 ; gain = 0.000 ; free physical = 52173 ; free virtual = 63169
INFO: [SYSTEM_LINK 82-52] Create top-level block diagram
INFO: [SYSTEM_LINK 82-38] [22:06:16] cf2bd started: /opt/Xilinx/Vitis/2020.2/bin/cf2bd  --linux --trace_buffer 1024 --input_file /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml --ip_db /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml --cf_name dr --working_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd --temp_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link --output_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int
INFO: [CF2BD 82-31] Launching cf2xd: cf2xd -linux -trace-buffer 1024 -i /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/cfgraph/cfgen_cfgraph.xml -r /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.cdb/xd_ip_db.xml -o dr.xml
INFO: [CF2BD 82-28] cf2xd finished successfully
INFO: [CF2BD 82-31] Launching cf_xsd: cf_xsd -disable-address-gen -dn dr -dp /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/sys_link/_sysl/.xsd
INFO: [CF2BD 82-28] cf_xsd finished successfully
INFO: [SYSTEM_LINK 82-37] [22:06:18] cf2bd finished successfully
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1621.238 ; gain = 0.000 ; free physical = 52167 ; free virtual = 63167
INFO: [v++ 60-1441] [22:06:18] Run run_link: Step system_link: Completed
Time (s): cpu = 00:00:09 ; elapsed = 00:00:08 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 52205 ; free virtual = 63206
INFO: [v++ 60-1443] [22:06:18] Run run_link: Step cf2sw: Started
INFO: [v++ 60-1453] Command Line: cf2sw -sdsl /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/sdsl.dat -rtd /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/cf2sw.rtd -nofilter /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/cf2sw_full.rtd -xclbin /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.1.xml
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [22:06:20] Run run_link: Step cf2sw: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 52205 ; free virtual = 63206
INFO: [v++ 60-1443] [22:06:20] Run run_link: Step rtd2_system_diagram: Started
INFO: [v++ 60-1453] Command Line: rtd2SystemDiagram
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [22:06:21] Run run_link: Step rtd2_system_diagram: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00.71 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 51998 ; free virtual = 63000
INFO: [v++ 60-1443] [22:06:21] Run run_link: Step vpl: Started
INFO: [v++ 60-1453] Command Line: vpl -t hw -f /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm --remote_ip_cache /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/ip_cache -s --output_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int --log_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link --report_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link --config /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/vplConfig.ini -k /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat --webtalk_flag Vitis --temp_dir /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link --no-info --iprepo /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/xo/ip_repo/xilinx_com_RTLKernel_DPUCZDX8G_1_0 --messageDb /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link/vpl.pb /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dr.bd.tcl
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link

****** vpl v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [VPL 60-839] Read in kernel information from file '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/kernel_info.dat'.
INFO: [VPL 60-423]   Target device: xilinx_zcu104_base_202020_1
INFO: [VPL 60-1032] Extracting hardware platform to /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/vivado/vpl/.local/hw_platform
WARNING: /opt/Xilinx/Vitis/2020.2/tps/lnx64/jre9.0.4 does not exist.
[22:06:29] Run vpl: Step create_project: Started
Creating Vivado project.
[22:06:33] Run vpl: Step create_project: Completed
[22:06:33] Run vpl: Step create_bd: Started
[22:06:40] Run vpl: Step create_bd: Completed
[22:06:40] Run vpl: Step update_bd: Started
[22:06:41] Run vpl: Step update_bd: Completed
[22:06:41] Run vpl: Step generate_target: Started
[22:07:09] Run vpl: Step generate_target: Completed
[22:07:09] Run vpl: Step config_hw_runs: Started
[22:07:09] Run vpl: Step config_hw_runs: Completed
[22:07:09] Run vpl: Step synth: Started
[22:07:40] Top-level synthesis in progress.
[22:08:02] Run vpl: Step synth: Completed
[22:08:02] Run vpl: Step impl: Started
[22:11:03] Finished 2nd of 6 tasks (FPGA linking synthesized kernels to platform). Elapsed time: 00h 04m 41s 

[22:11:03] Starting logic optimization..
[22:11:03] Phase 1 Retarget
[22:11:03] Phase 2 Constant propagation
[22:11:33] Phase 3 BUFG optimization
[22:11:33] Phase 4 Shift Register Optimization
[22:11:33] Phase 5 Sweep
[22:11:33] Phase 6 Constant propagation
[22:11:33] Phase 7 Sweep
[22:11:33] Phase 8 Remap
[22:12:03] Phase 9 Post Processing Netlist
[22:12:33] Finished 3rd of 6 tasks (FPGA logic optimization). Elapsed time: 00h 01m 30s 

[22:12:33] Starting logic placement..
[22:12:33] Phase 1 Placer Initialization
[22:12:33] Phase 1.1 Placer Initialization Netlist Sorting
[22:12:33] Phase 1.2 IO Placement/ Clock Placement/ Build Placer Device
[22:13:03] Phase 1.3 Build Placer Netlist Model
[22:13:33] Phase 1.4 Constrain Clocks/Macros
[22:13:33] Phase 2 Global Placement
[22:13:33] Phase 2.1 Floorplanning
[22:13:33] Phase 2.1.1 Partition Driven Placement
[22:13:33] Phase 2.1.1.1 PBP: Partition Driven Placement
[22:15:03] Phase 2.1.1.2 PBP: Clock Region Placement
[22:15:03] Phase 2.1.1.3 PBP: Discrete Incremental
[22:15:03] Phase 2.1.1.4 PBP: Compute Congestion
[22:15:03] Phase 2.1.1.5 PBP: Macro Placement
[22:15:33] Phase 2.1.1.6 PBP: UpdateTiming
[22:15:33] Phase 2.1.1.7 PBP: Add part constraints
[22:15:33] Phase 2.2 Update Timing before SLR Path Opt
[22:15:33] Phase 2.3 Global Placement Core
[22:17:34] Phase 2.3.1 Physical Synthesis In Placer
[22:19:34] Phase 3 Detail Placement
[22:19:34] Phase 3.1 Commit Multi Column Macros
[22:19:34] Phase 3.2 Commit Most Macros & LUTRAMs
[22:20:34] Phase 3.3 Small Shape DP
[22:20:34] Phase 3.3.1 Small Shape Clustering
[22:20:34] Phase 3.3.2 Flow Legalize Slice Clusters
[22:20:34] Phase 3.3.3 Slice Area Swap
[22:21:04] Phase 3.4 Re-assign LUT pins
[22:21:34] Phase 3.5 Pipeline Register Optimization
[22:21:34] Phase 3.6 Fast Optimization
[22:22:04] Phase 4 Post Placement Optimization and Clean-Up
[22:22:04] Phase 4.1 Post Commit Optimization
[22:22:35] Phase 4.1.1 Post Placement Optimization
[22:22:35] Phase 4.1.1.1 BUFG Insertion
[22:22:35] Phase 1 Physical Synthesis Initialization
[22:23:05] Phase 4.2 Post Placement Cleanup
[22:23:35] Phase 4.3 Placer Reporting
[22:23:35] Phase 4.3.1 Print Estimated Congestion
[22:23:35] Phase 4.4 Final Placement Cleanup
[22:24:05] Finished 4th of 6 tasks (FPGA logic placement). Elapsed time: 00h 11m 31s 

[22:24:05] Starting logic routing..
[22:24:35] Phase 1 Build RT Design
[22:24:35] Phase 2 Router Initialization
[22:24:35] Phase 2.1 Fix Topology Constraints
[22:24:35] Phase 2.2 Pre Route Cleanup
[22:24:35] Phase 2.3 Global Clock Net Routing
[22:25:05] Phase 2.4 Update Timing
[22:26:05] Phase 3 Initial Routing
[22:26:05] Phase 3.1 Global Routing
[22:26:35] Phase 4 Rip-up And Reroute
[22:26:35] Phase 4.1 Global Iteration 0
[22:33:06] Phase 4.2 Global Iteration 1
[22:33:36] Phase 5 Delay and Skew Optimization
[22:33:36] Phase 5.1 TNS Cleanup
[22:33:36] Phase 5.1.1 Delay CleanUp
[22:33:36] Phase 5.1.1.1 Update Timing
[22:34:06] Phase 5.2 Clock Skew Optimization
[22:34:06] Phase 6 Post Hold Fix
[22:34:06] Phase 6.1 Hold Fix Iter
[22:34:06] Phase 6.1.1 Update Timing
[22:34:06] Phase 7 Route finalize
[22:34:06] Phase 8 Verifying routed nets
[22:34:06] Phase 9 Depositing Routes
[22:34:37] Phase 10 Route finalize
[22:34:37] Phase 11 Post Router Timing
[22:35:07] Finished 5th of 6 tasks (FPGA routing). Elapsed time: 00h 11m 01s 

[22:35:07] Starting bitstream generation..
Starting optional post-route physical design optimization.
Finished optional post-route physical design optimization.
[22:38:07] Creating bitmap...
[22:38:20] Run vpl: Step impl: Completed
[22:38:21] Writing bitstream ./xilinx_zcu104_base_wrapper.bit...
[22:38:21] Finished 6th of 6 tasks (FPGA bitstream generation). Elapsed time: 00h 03m 14s 
[22:38:21] Run vpl: FINISHED. Run Status: impl Complete!
INFO: [v++ 60-1441] [22:38:21] Run run_link: Step vpl: Completed
Time (s): cpu = 00:00:07 ; elapsed = 00:32:01 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 42112 ; free virtual = 61056
INFO: [v++ 60-1443] [22:38:21] Run run_link: Step rtdgen: Started
INFO: [v++ 60-1453] Command Line: rtdgen
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1453] Command Line: cf2sw -a /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/address_map.xml -sdsl /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/sdsl.dat -xclbin /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/xclbin_orig.xml -rtd /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml
INFO: [v++ 60-1652] Cf2sw returned exit code: 0
INFO: [v++ 60-2311] HPISystemDiagram::writeSystemDiagramAfterRunningVivado, rtdInputFilePath: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd
INFO: [v++ 60-2312] HPISystemDiagram::writeSystemDiagramAfterRunningVivado, systemDiagramOutputFilePath: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json
INFO: [v++ 60-1618] Launching 
INFO: [v++ 60-1441] [22:38:23] Run run_link: Step rtdgen: Completed
Time (s): cpu = 00:00:02 ; elapsed = 00:00:02 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 42113 ; free virtual = 61058
INFO: [v++ 60-1443] [22:38:23] Run run_link: Step xclbinutil: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --add-section BITSTREAM:RAW:/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/system.bit --force --target hw --key-value SYS:dfx_enable:false --add-section :JSON:/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.rtd --add-section CLOCK_FREQ_TOPOLOGY:JSON:/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_xml.rtd --add-section BUILD_METADATA:JSON:/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_build.rtd --add-section EMBEDDED_METADATA:RAW:/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml --add-section SYSTEM_METADATA:RAW:/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json --key-value SYS:PlatformVBNV:xilinx.com_xd_xilinx_zcu104_base_202020_1_202020_1 --output /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
XRT Build Version: 2.8.0 (Vitis)
       Build Date: 2020-11-04 13:51:01
          Hash ID: 70b0d7e5db97d08503f97ca713c33ecb01ddca64
Creating a default 'in-memory' xclbin image.

Section: 'BITSTREAM'(0) was successfully added.
Size   : 19311223 bytes
Format : RAW
File   : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/system.bit'

Section: 'MEM_TOPOLOGY'(6) was successfully added.
Format : JSON
File   : 'mem_topology'

Section: 'IP_LAYOUT'(8) was successfully added.
Format : JSON
File   : 'ip_layout'

Section: 'CONNECTIVITY'(7) was successfully added.
Format : JSON
File   : 'connectivity'
WARNING: Skipping CLOCK_FREQ_TOPOLOGY section for count size is zero.
WARNING: Section 'CLOCK_FREQ_TOPOLOGY' content is empty.  No data in the given JSON file.

Section: 'CLOCK_FREQ_TOPOLOGY'(11) was empty.  No action taken.
Format : JSON
File   : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_xml.rtd'

Section: 'BUILD_METADATA'(14) was successfully added.
Size   : 4854 bytes
Format : JSON
File   : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu_build.rtd'

Section: 'EMBEDDED_METADATA'(2) was successfully added.
Size   : 5262 bytes
Format : RAW
File   : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/dpu.xml'

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 16982 bytes
Format : RAW
File   : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/int/systemDiagramModelSlrBaseAddress.json'
Successfully wrote (19352708 bytes) to the output file: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin
Leaving xclbinutil.
INFO: [v++ 60-1441] [22:38:24] Run run_link: Step xclbinutil: Completed
Time (s): cpu = 00:00:00.66 ; elapsed = 00:00:00.69 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 43001 ; free virtual = 61966
INFO: [v++ 60-1443] [22:38:24] Run run_link: Step xclbinutilinfo: Started
INFO: [v++ 60-1453] Command Line: xclbinutil --quiet --force --info /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin.info --input /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [22:38:25] Run run_link: Step xclbinutilinfo: Completed
Time (s): cpu = 00:00:00.73 ; elapsed = 00:00:00.77 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 43005 ; free virtual = 61967
INFO: [v++ 60-1443] [22:38:25] Run run_link: Step generate_sc_driver: Started
INFO: [v++ 60-1453] Command Line: 
INFO: [v++ 60-1454] Run Directory: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/link/run_link
INFO: [v++ 60-1441] [22:38:25] Run run_link: Step generate_sc_driver: Completed
Time (s): cpu = 00:00:00 ; elapsed = 00:00:00 . Memory (MB): peak = 1579.098 ; gain = 0.000 ; free physical = 43005 ; free virtual = 61967
INFO: [v++ 60-244] Generating system estimate report...
INFO: [v++ 60-1092] Generated system estimate report: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link/system_estimate_dpu.xtxt
INFO: [v++ 60-2397] Platform default or user specified output type sd_card detected but is not a supported output for v++ --link. Use the v++ --package option instead to create SD card output.
INFO: [v++ 60-586] Created binary_container_1/dpu.xclbin
INFO: [v++ 60-1307] Run completed. Additional information can be found in:
    Guidance: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link/v++_link_dpu_guidance.html
    Timing Report: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/reports/link/imp/impl_1_xilinx_zcu104_base_wrapper_timing_summary_routed.rpt
    Vivado Log: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link/vivado.log
    Steps Log File: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/logs/link/link.steps.log

INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/dpu.xclbin.link_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 32m 25s
INFO: [v++ 60-1653] Closing dispatch client.
v++ -t hw --platform ./xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm -p binary_container_1/dpu.xclbin  -o dpu.xclbin --package.out_dir binary_container_1 --package.rootfs ./xilinx-zynqmp-common-v2020.2/rootfs.ext4 --package.sd_file ./xilinx-zynqmp-common-v2020.2/Image 
Option Map File Used: '/opt/Xilinx/Vitis/2020.2/data/vitis/vpp/optMap.xml'

****** v++ v2020.2 (64-bit)
  **** SW Build (by xbuild) on 2020-11-18-05:13:29
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

INFO: [v++ 60-1306] Additional information associated with this v++ package can be found at:
    Reports: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/_x/reports/package
    Log files: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/_x/logs/package
Running Dispatch Server on port:35639
INFO: [v++ 60-1548] Creating build summary session with primary output /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu.xclbin.package_summary, at Mon Jan 11 22:38:36 2021
INFO: [v++ 60-1316] Initiating connection to rulecheck server, at Mon Jan 11 22:38:36 2021
Running Rule Check Server on port:45495
INFO: [v++ 60-1315] Creating rulecheck session with output '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/_x/reports/package/v++_package_dpu_guidance.html', at Mon Jan 11 22:38:37 2021
INFO: [v++ 60-895]   Target platform: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/xilinx_zcu104_base_202020_1.xpfm
INFO: [v++ 60-1578]   This platform contains Xilinx Shell Archive '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx_zcu104_base_202020_1/hw/xilinx_zcu104_base_202020_1.xsa'
INFO: [v++ 60-2256] Packaging for hardware

Section: 'SYSTEM_METADATA'(22) was successfully written.
Format: RAW
File  : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/_x/package/extractedSystemDiagram.json'

Section: 'BITSTREAM'(0) was successfully written.
Format: RAW
File  : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/_x/package/system.bit'
WARNING: [v++ 82-1147] Kernel image is not specified for linux domain
INFO: [v++ 82-1025] generating bootimage

****** Xilinx Bootgen v2020.2
  **** Build date : Nov 18 2020-09:50:31
    ** Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.

[WARNING]: [fsbl_config] a53_x64 | a53_x32 | r5_single | r5_dual is no more supported. Use 'destination_cpu' attribute for bootloader partition

[INFO]   : Bootimage generated successfully

INFO: [v++ 82-1011] creating sd_card directory
INFO: [v++ 82-3558] mkfsimage command run: /opt/Xilinx/Vitis/2020.2/scripts/vitis/util/mkfsImage.sh -s /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/sd_card/ -o /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/binary_container_1/sd_card.img -e /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/xilinx-zynqmp-common-v2020.2/rootfs.ext4
FATSIZE:1024
fat_start:63
fat_end:2096639
fat_sector:2096577
ext4_start:0
ext4_sector:4833104
EXT4SIZE:2560
TOTALSIZE:3584
dummy_ext4_sector:409776
sd_card_fat_start:2048
sd_card_ext4_start:2000896
dummy_ext4_start:6834000
2096577+0 レコード入力
2096577+0 レコード出力
1073447424 bytes (1.1 GB, 1.0 GiB) copied, 1.97995 s, 542 MB/s
4833104+0 レコード入力
4833104+0 レコード出力
2474549248 bytes (2.5 GB, 2.3 GiB) copied, 4.97146 s, 498 MB/s
409776+0 レコード入力
409776+0 レコード出力
209805312 bytes (210 MB, 200 MiB) copied, 0.348587 s, 602 MB/s

Section: 'SYSTEM_METADATA'(22) was successfully added.
Size   : 17018 bytes
Format : RAW
File   : '/home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/_x/package/packagedSystemDiagram.json'
Successfully wrote (19352748 bytes) to the output file: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/_x/package/upsert.xclbin
INFO: [v++ 60-2460] Successfully copied a temporary xclbin to the output xclbin: /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu.xclbin
INFO: [v++ 60-2343] Use the vitis_analyzer tool to visualize and navigate the relevant reports. Run the following command. 
    vitis_analyzer /home/hidemi/workspace/VitisAI/VitisAI_2020.2/Vitis-AI/dsa/DPU-TRD/prj/Vitis/dpu.xclbin.package_summary 
INFO: [v++ 60-791] Total elapsed time: 0h 0m 24s
INFO: [v++ 60-1653] Closing dispatch client.
cp ./binary_*/link/vivado/vpl/prj/prj*/sources_1/bd/*/hw_handoff/*.hwh ./binary_*/sd_card
cp ./binary_*/link/vivado/vpl/prj/prj.gen/sources_1/bd/*/ip/*_DPUCZDX8G_1_0/arch.json ./binary_*/sd_card

マジかぁ〜!!!

ビルドできた。

これが答えか…。

(そして、このブログの草案を書いたところにACRiの記事が降ってきた)

(なんか、狙ったかのようなオチなのか?)

write: 2021/01/19/ 00:00:00