ひでみのアイデア帳

くだらないことなんだけど、忘れないために・・・

SDSoC環境入門してみた

せっかく、SDSoCのライセンスも入手出来たのでXilinx社のドキュメント(UG1028)を参考に進めてみた。

Ubuntu 16.04で試してみた結果である。 SDSoCはUbuntu 14.04でサポートしていることを承知の上で進めている。

サンプル アプリケーションのビルドと実行(p.15)を参考にしつつ、サンプルコードをmakeしてみた。 とりあえず、mmultをコピーして試してみた。

% cp -R /opt/Xilinx/SDSoC/2016.2/samples/mmult .
% cd mmult

早速、makeするとエラーが出た。 libgcrypt.so.11が無いというエラーが発生する。

% make
sds++ -sds-pf zc702 -sds-hw mmult_accel mmult_accel.cpp -sds-end -poll-mode 1 -Wall -O3 -c -MMD -MP -MF"mmult.d" mmult.cpp -o mmult.o
xsltproc: error while loading shared libraries: libgcrypt.so.11: cannot open shared object file: No such file or directory
xsltproc: error while loading shared libraries: libgcrypt.so.11: cannot open shared object file: No such file or directory
Usage: /usr/bin/which [-a] args
Illegal option -g
    while executing
"exec which [apc_get_global APCC_TOOLCHAIN]-g++"
    (procedure "sdscc_set_toolchain_config" line 27)
    invoked from within
"sdscc_set_toolchain_config "zynq" "linux" "cortex-a9" "arm-linaro""
    invoked from within
"if { [string match $target_os_type "linux"] } {
  if {[string first "zcu102" $xsd_platform] >= 0} {
    apc_set_global APCC_PROC_INSTANCE psu_cortexa5..."
    (file "/opt/Xilinx/SDSoC/2016.2/bin/xdcc.tcl" line 2984)
Makefile:65: ターゲット 'mmult.o' のレシピで失敗しました
make: *** [mmult.o] エラー 1

Ubuntu 16.04にはlibgcrypt.so.20がインストールされているんだよなぁ。

% find /lib | grep libgcrypt
/lib/x86_64-linux-gnu/libgcrypt.so.20.0.5
/lib/x86_64-linux-gnu/libgcrypt.so.20

あまり、インストール物を増やしたくないので正攻法ではなくて、いつもように俺々環境を構築してみる。

libgcrypt.so.11のインストール

これだけは追加インストールした。

% wget http://ftp.acc.umu.se/mirror/cdimage/snapshot/Debian/pool/main/libg/libgcrypt11/libgcrypt11_1.5.3-5_amd64.deb
% sudo dpkg -i libgcrypt11_1.5.3-5_amd64.deb

はい、これでlibgcrypt.so.11がインストールされました。

% find /lib | grep libgcrypt
/lib/x86_64-linux-gnu/libgcrypt.so.20.0.5
/lib/x86_64-linux-gnu/libgcrypt.so.11.8.2
/lib/x86_64-linux-gnu/libgcrypt.so.11
/lib/x86_64-linux-gnu/libgcrypt.so.20

もう一度、makeに挑戦!

再びエラー発生。

% make
sds++ -sds-pf zc702 -sds-hw mmult_accel mmult_accel.cpp -sds-end -poll-mode 1 -Wall -O3 -c -MMD -MP -MF"mmult.d" mmult.cpp -o mmult.o
xsltproc: /opt/Xilinx/SDSoC/2016.2/lib/lnx64.o/libstdc++.so.6: version `CXXABI_1.3.8' not found (required by /usr/lib/x86_64-linux-gnu/libicuuc.so.55)
xsltproc: /opt/Xilinx/SDSoC/2016.2/lib/lnx64.o/libstdc++.so.6: version `CXXABI_1.3.8' not found (required by /usr/lib/x86_64-linux-gnu/libicuuc.so.55)
Usage: /usr/bin/which [-a] args
Illegal option -g
    while executing
"exec which [apc_get_global APCC_TOOLCHAIN]-g++"
    (procedure "sdscc_set_toolchain_config" line 27)
    invoked from within
"sdscc_set_toolchain_config "zynq" "linux" "cortex-a9" "arm-linaro""
    invoked from within
"if { [string match $target_os_type "linux"] } {
  if {[string first "zcu102" $xsd_platform] >= 0} {
    apc_set_global APCC_PROC_INSTANCE psu_cortexa5..."
    (file "/opt/Xilinx/SDSoC/2016.2/bin/xdcc.tcl" line 2984)
Makefile:65: ターゲット 'mmult.o' のレシピで失敗しました
make: *** [mmult.o] エラー 1

次のエラーは/opt/Xilinx/SDSoC/2016.2/lib/lnx64.o/libstdc++.so.6に`CXXABI_1.3.8'のバージョンが無いというエラーである。 Webで調べるとgcc/g++を4.9系に戻すことがソリューションらしい。

そう言えば、SDSoCはgcc 4.9系だっけ?

LLVMだと思ってたんだけど、そうじゃないらしい・・・。

Ubuntu 16.04は次のように5.4系である。

% gcc --version
gcc (Ubuntu 5.4.0-6ubuntu1~16.04.2) 5.4.0 20160609
Copyright (C) 2015 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

当然、ここで欲が出ます。 ここで4.9系には戻したくないなぁ。 二重管理も嫌だなぁ・・・

と、いうことでlibstdc++.so.6のリンク先を変更する。

% cd /opt/Xilinx/SDSoC/2016.2/lib/lnx64.o
% mv libstdc++.so.6 libstdc++.so.6.org
% sudo ln -s /usr/lib/x86_64-linux-gnu/libstdc++.so.6

そして、再びmake。

そういえば、忘れてたけど初めての環境だとgmakeもリンクを貼っておいたほうが良いよ。

% ln -s /usr/bin/make /usr/bin/gmake

本題に戻って、makeする。 っうか、いつもながらXilinx社のツールはハマりどころ満載で面白い。

% date;make;date
2016年  9月 22日 木曜日 16:16:41 JST
sds++ -sds-pf zc702 -sds-hw mmult_accel mmult_accel.cpp -sds-end -poll-mode 1 -Wall -O3 -c -MMD -MP -MF"mmult.d" mmult.cpp -o mmult.o
INFO: [SDSoC 0-0] Create data motion intermediate representation
INFO: [SDSoC 0-0] Compiling /home/hidemi/temp/mmult/mmult.cpp
sds++ log file saved as /home/hidemi/temp/mmult/_sds/reports/sds_mmult.log

sds++ -sds-pf zc702 -sds-hw mmult_accel mmult_accel.cpp -sds-end -poll-mode 1 -Wall -O3 -c -MMD -MP -MF"mmult_accel.d" mmult_accel.cpp -o mmult_accel.o
INFO: [SDSoC 0-0] Processing -sds-hw block for mmult_accel
INFO: [SDSoC 0-0] Create data motion intermediate representation
INFO: [SDSoC 0-0] Performing accelerator source linting for mmult_accel
INFO: [SDSoC 0-0] Performing pragma generation
INFO: [SDSoC 0-0] Successfully generated tcl script: /home/hidemi/temp/mmult/_sds/vhls/mmult_accel.tcl
INFO: [SDSoC 0-0] Moving function mmult_accel to Programmable Logic
sds++ log file saved as /home/hidemi/temp/mmult/_sds/reports/sds_mmult_accel.log

sds++ -sds-pf zc702 -sds-hw mmult_accel mmult_accel.cpp -sds-end -poll-mode 1 -O3 mmult.o mmult_accel.o -o mmult.elf
INFO: [SDSoC 0-0] Analyzing object files
... /home/hidemi/temp/mmult/mmult.o
... /home/hidemi/temp/mmult/mmult_accel.o
INFO: [SDSoC 0-0] Generating data motion network
INFO: [SDSoC 0-0] Analyzing hardware accelerators...
INFO: [SDSoC 0-0] Analyzing callers to hardware accelerators...
INFO: [SDSoC 0-0] Scheduling data transfer graph for partition 0
INFO: [SDSoC 0-0] Creating data motion network hardware for partition 0
INFO: [SDSoC 0-0] Creating software stub functions for partition 0
INFO: [SDSoC 0-0] Generating data motion network report for partition 0
INFO: [SDSoC 0-0] Rewriting caller code
INFO: [SDSoC 0-0] Creating block diagram (BD), address map, port information and device registration for partition 0 (this may take a few minutes)
system_linker started at Thu Sep 22 16:17:54 JST 2016
INFO: [SDSoC 0-0] Copying address map
INFO: [SDSoC 0-0] Creating port and device registration data
system_linker completed at Thu Sep 22 16:19:28 JST 2016
INFO: [SDSoC 0-0] Rewrite caller functions
INFO: [SDSoC 0-0] Compile caller rewrite file /home/hidemi/temp/mmult/_sds/swstubs/mmult.cpp
INFO: [SDSoC 0-0] Prepare hardware access API functions
INFO: [SDSoC 0-0] Create accelerator stub functions
INFO: [SDSoC 0-0] Compile hardware access API functions
INFO: [SDSoC 0-0] Compile accelerator stub functions
INFO: [SDSoC 0-0] Link application ELF file
INFO: [SDSoC 0-0] Enable generation of hardware programming files
INFO: [SDSoC 0-0] Enable generation of boot files
INFO: [SDSoC 0-0] Calling system_linker for partition 0
system_linker started at Thu Sep 22 16:19:29 JST 2016
INFO: [SDSoC 0-0] Generating bitstream for platform zc702.
      This may take some time to complete
... [16:34:30] Starting synth_design
... [16:34:40] Starting RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1147.230 ; gain = 254.262 ; free physical = 623 ; free virtual = 5830
... [16:34:55] Start Loading Part and Timing Information
... [16:34:55] Start Applying 'set_property' XDC Constraints
... [16:34:55] Start RTL Component Statistics
... [16:34:55] Start RTL Hierarchical Component Statistics
... [16:34:55] Start Part Resource Summary
... [16:35:00] Start Parallel Synthesis Optimization  : Time (s): cpu = 00:00:36 ; elapsed = 00:00:38 . Memory (MB): peak = 1512.168 ; gain = 619.199 ; free physical = 336 ; free virtual = 5589
... [16:35:00] Start Cross Boundary Optimization
... [16:35:00] Start Area Optimization
... [16:35:00] Start Timing Optimization
... [16:35:10] Start Applying XDC Timing Constraints
... [16:35:10] Start Technology Mapping
... [16:35:10] Start IO Insertion
... [16:35:10] Start Flattening Before IO Insertion
... [16:35:10] Start Final Netlist Cleanup
... [16:35:10] Start Renaming Generated Instances
... [16:35:10] Start Rebuilding User Hierarchy
... [16:35:10] Start Renaming Generated Ports
... [16:35:10] Start Handling Custom Attributes
... [16:35:10] Start Renaming Generated Nets
... [16:35:10] Start Writing Synthesis Report
CRITICAL WARNING: [Pfi 67-13] Hardware Handoff file zc702_processing_system7_1_0.hwdef does not exist for instance zc702_i/ps7/inst
INFO: [SDSoC 0-0] See /home/hidemi/temp/mmult/_sds/p0/ipi/vivado.log for the context of the Vivado message above.
... [16:36:03] Starting DRC Task
... [16:36:23] Starting Logic Optimization Task
... [16:36:48] Starting Connectivity Check Task
... [16:36:48] Starting Power Optimization Task
... [16:37:18] Starting PowerOpt Patch Enables Task
... [16:37:44] Starting Placer Task
... [16:40:35] Starting Routing Task
INFO: [SDSoC 0-0] Creating boot files
system_linker completed at Thu Sep 22 16:43:57 JST 2016
All user specified timing constraints are met.
sds++ log file saved as /home/hidemi/temp/mmult/_sds/reports/sds.log

2016年  9月 22日 木曜日 16:43:57 JST

さて、なんでdateを挟んだのでしょう。 実行時間を見たかったからです。Core2Duoで約30分ですね。 そりゃ、コンパイル時間が長いと言うわね。

でも、mmultはzc702向けだった。 あとで、Zybo向けの結果もあるので・・・

成果物はこんな感じなのね・・・

% ls -al sd_card/
合計 12820
drwxrwxr-x 3 hidemi hidemi    4096  9月 22 16:43 .
drwxr-xr-x 4 hidemi hidemi    4096  9月 22 16:43 ..
-rw-rw-r-- 1 hidemi hidemi 4518108  9月 22 16:43 BOOT.BIN
-rw-rw-r-- 1 hidemi hidemi     369  9月 22 16:43 README.txt
drwxrwxr-x 2 hidemi hidemi    4096  9月 22 16:43 _sds
-rw-r--r-- 1 hidemi hidemi   10833  7月 16 10:20 devicetree.dtb
-rwxrwxr-x 1 hidemi hidemi   54871  9月 22 16:19 mmult.elf
-rw-r--r-- 1 hidemi hidemi 3614008  7月 16 10:20 uImage
-rwxr-xr-x 1 hidemi hidemi 4901940  7月 16 10:20 uramdisk.image.gz

今度はZybo向け。

% date;make;date
2016年  9月 22日 木曜日 16:59:10 JST
sds++ -sds-pf zybo -sds-hw mmult_accel mmult.cpp -sds-end  -Wall -O3 -c -MMD -MP -MF"main.d" main.cpp -o main.o
INFO: [SDSoC 0-0] Create data motion intermediate representation
INFO: [SDSoC 0-0] Compiling /home/hidemi/temp/mmult_xc7z010/main.cpp
sds++ log file saved as /home/hidemi/temp/mmult_xc7z010/_sds/reports/sds_main.log

sds++ -sds-pf zybo -sds-hw mmult_accel mmult.cpp -sds-end  -Wall -O3 -c -MMD -MP -MF"mmult.d" mmult.cpp -o mmult.o
INFO: [SDSoC 0-0] Processing -sds-hw block for mmult_accel
INFO: [SDSoC 0-0] Create data motion intermediate representation
INFO: [SDSoC 0-0] Performing accelerator source linting for mmult_accel
INFO: [SDSoC 0-0] Performing pragma generation
INFO: [SDSoC 0-0] Successfully generated tcl script: /home/hidemi/temp/mmult_xc7z010/_sds/vhls/mmult_accel.tcl
INFO: [SDSoC 0-0] Moving function mmult_accel to Programmable Logic
sds++ log file saved as /home/hidemi/temp/mmult_xc7z010/_sds/reports/sds_mmult.log

sds++ -sds-pf zybo -sds-hw mmult_accel mmult.cpp -sds-end  -O3 -poll-mode 1 main.o mmult.o -o mmult_xc7z010.elf
INFO: [SDSoC 0-0] Analyzing object files
... /home/hidemi/temp/mmult_xc7z010/main.o
... /home/hidemi/temp/mmult_xc7z010/mmult.o
INFO: [SDSoC 0-0] Generating data motion network
INFO: [SDSoC 0-0] Analyzing hardware accelerators...
INFO: [SDSoC 0-0] Analyzing callers to hardware accelerators...
INFO: [SDSoC 0-0] Scheduling data transfer graph for partition 0
INFO: [SDSoC 0-0] Creating data motion network hardware for partition 0
INFO: [SDSoC 0-0] Creating software stub functions for partition 0
INFO: [SDSoC 0-0] Generating data motion network report for partition 0
INFO: [SDSoC 0-0] Rewriting caller code
INFO: [SDSoC 0-0] Creating block diagram (BD), address map, port information and device registration for partition 0 (this may take a few minutes)
system_linker started at Thu Sep 22 17:00:20 JST 2016
INFO: [SDSoC 0-0] Copying address map
INFO: [SDSoC 0-0] Creating port and device registration data
system_linker completed at Thu Sep 22 17:01:47 JST 2016
INFO: [SDSoC 0-0] Rewrite caller functions
INFO: [SDSoC 0-0] Compile caller rewrite file /home/hidemi/temp/mmult_xc7z010/_sds/swstubs/main.cpp
INFO: [SDSoC 0-0] Prepare hardware access API functions
INFO: [SDSoC 0-0] Create accelerator stub functions
INFO: [SDSoC 0-0] Compile hardware access API functions
INFO: [SDSoC 0-0] Compile accelerator stub functions
INFO: [SDSoC 0-0] Link application ELF file
INFO: [SDSoC 0-0] Enable generation of hardware programming files
INFO: [SDSoC 0-0] Enable generation of boot files
INFO: [SDSoC 0-0] Calling system_linker for partition 0
system_linker started at Thu Sep 22 17:01:49 JST 2016
INFO: [SDSoC 0-0] Generating bitstream for platform zybo.
      This may take some time to complete
... [17:14:22] Starting synth_design
... [17:14:32] Starting RTL Elaboration : Time (s): cpu = 00:00:17 ; elapsed = 00:00:18 . Memory (MB): peak = 1147.219 ; gain = 254.246 ; free physical = 722 ; free virtual = 5991
... [17:14:47] Start Loading Part and Timing Information
... [17:14:47] Start Applying 'set_property' XDC Constraints
... [17:14:47] Start RTL Component Statistics
... [17:14:47] Start RTL Hierarchical Component Statistics
... [17:14:47] Start Part Resource Summary
... [17:14:47] Start Parallel Synthesis Optimization  : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 1491.812 ; gain = 598.840 ; free physical = 440 ; free virtual = 5709
... [17:14:47] Start Cross Boundary Optimization
... [17:14:47] Start Area Optimization
... [17:14:47] Start Timing Optimization
... [17:15:02] Start Applying XDC Timing Constraints
... [17:15:02] Start Technology Mapping
... [17:15:02] Start IO Insertion
... [17:15:02] Start Flattening Before IO Insertion
... [17:15:02] Start Final Netlist Cleanup
... [17:15:02] Start Renaming Generated Instances
... [17:15:02] Start Rebuilding User Hierarchy
... [17:15:02] Start Renaming Generated Ports
... [17:15:02] Start Handling Custom Attributes
... [17:15:02] Start Renaming Generated Nets
... [17:15:02] Start Writing Synthesis Report
CRITICAL WARNING: [Pfi 67-13] Hardware Handoff file zybo_ps7_0.hwdef does not exist for instance zybo_i/ps7/inst
INFO: [SDSoC 0-0] See /home/hidemi/temp/mmult_xc7z010/_sds/p0/ipi/vivado.log for the context of the Vivado message above.
... [17:15:50] Starting DRC Task
... [17:16:05] Starting Logic Optimization Task
... [17:16:20] Starting Connectivity Check Task
... [17:16:25] Starting Power Optimization Task
... [17:16:35] Starting PowerOpt Patch Enables Task
... [17:16:56] Starting Placer Task
... [17:19:12] Starting Routing Task
INFO: [SDSoC 0-0] Creating boot files
system_linker completed at Thu Sep 22 17:21:38 JST 2016
All user specified timing constraints are met.
sds++ log file saved as /home/hidemi/temp/mmult_xc7z010/_sds/reports/sds.log

2016年  9月 22日 木曜日 17:21:38 JST

約20分・・・。 たしかに、ソフトウェアのコンパイルってことになると遅いよね。 これで不具合無くFPGAで実行できて従来のソフトウェアだけよりも速くできるなら約20分なんて、なんでもない時間だと思う。 デバッグしようとするからこの時間が長く感じられるんだなぁ。

ここでデバッグすることを念頭に置いてることが高位合成においてナンセンスすぎる。 高位合成をかける時点で、不具合やバグは無いものだし高位合成後は不具合は発生しないことが前提じゃないと高位合成なんてする意味無いよ。 そもそもC/C++のコード自体をデバッグしてから高位合成にいどんでるんでしょ? 変な工数ばかり増やすだけでTATも減らなくないっての意味がない。

高位合成して不具合が出るソースコードはそもそもというか作り手、ソースコードを書いた人そのものが不具合でしょ。 だって、高位合成できないソースコードを書くんだから・・・。

それで、元に戻って生成物はこんな感じ。

% ls -al sd_card/
合計 10904
drwxrwxr-x 3 hidemi hidemi    4096  9月 22 17:21 .
drwxr-xr-x 4 hidemi hidemi    4096  9月 22 17:21 ..
-rw-rw-r-- 1 hidemi hidemi 2556368  9月 22 17:21 BOOT.BIN
-rw-rw-r-- 1 hidemi hidemi     230  9月 22 17:21 README.txt
drwxrwxr-x 2 hidemi hidemi    4096  9月 22 17:21 _sds
-rw-r--r-- 1 hidemi hidemi    8442  7月 16 10:20 devicetree.dtb
-rwxrwxr-x 1 hidemi hidemi   54864  9月 22 17:01 mmult_xc7z010.elf
-rw-r--r-- 1 hidemi hidemi 3614008  7月 16 10:20 uImage
-rwxr-xr-x 1 hidemi hidemi 4901940  7月 16 10:20 uramdisk.image.gz

とりあえず、SDSoCを試しただけなので、今日はここまで。 次は実機で動作させてみる。