SystemVerilogお勉強(5)

task使えないのね

task使えないのは痛いのかな？

exportを元に細工してみた。

function.c

#include "dpi.h"

int cFunc(int x)
{
  int rslt;
  printf("[cFunc] %08x\n", x);
  rslt = svPrintTaskEnable();
  printf("svPrintTaskEnable(%d)\n", rslt);
  return svFunc(x) ;
}

file.sv

module TOP();

  export "DPI-C" function svFunc ;
  export "DPI-C" function svPrintTaskEnable ;

  int svValue ;

  function int svFunc(input int x) ;
    svValue = x + 1 ;
    return svValue + 3 ;
  endfunction

  task PrintTask;
  begin
    $display("[PrintTask] svValue: %x", svValue);
  end
  endtask

  reg TaskEnable = 0;
  function int svPrintTaskEnable() ;
    TaskEnable = 1;
    return  0;
  endfunction

  always begin
    wait(TaskEnable == 1);
    PrintTask();
    TaskEnable = 0;
  end

  import "DPI-C" function int cFunc(input int x) ;

  int result ;

  initial
  begin
    svValue = 15 ;
    result = cFunc(3) ;
    if (svValue != 4)
    begin
      $display("FAILED") ;
      $finish ;
    end
    if (result == 7)
      $display("PASSED") ;
    else
      $display("FAILED") ;
  end

endmodule

いざ、実行！

以下、結果。

$ xvlog -sv file.sv
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/simple_export/file.sv" into library work
INFO: [VRFC 10-311] analyzing module TOP
$ xelab TOP -dpiheader dpi.h
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab TOP -dpiheader dpi.h
Multi-threading is on. Using 10 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Exiting after writing out the dpi header file dpi.h.
$ xsc function.c
Multi-threading is on. Using 10 slave threads.
Running compilation flow
Done compilation
Done linking: "/simple_export/xsim.dir/xsc/dpi.so"
$ xelab TOP -sv_lib dpi -R
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: /opt/Xilinx/Vivado/2017.2/bin/unwrapped/lnx64.o/xelab TOP -sv_lib dpi -R
Multi-threading is on. Using 10 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module work.TOP
Built simulation snapshot work.TOP

****** xsim v2017.2 (64-bit)
  **** SW Build 1909853 on Thu Jun 15 18:39:10 MDT 2017
  **** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
    ** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.

source xsim.dir/work.TOP/xsim_script.tcl
# xsim {work.TOP} -autoloadwcfg -runall
Vivado Simulator 2017.2
Time resolution is 1 ps
run -all
[cFunc] 00000003
svPrintTaskEnable(0)
PASSED
[PrintTask] svValue: 00000004
exit
INFO: [Common 17-206] Exiting xsim at Mon Jul 31 13:56:23 2017...
$

まぁ、実行されるタイミングがどうであれ、taskをループして、SystemVerilogのfunctionでEnableで立ち上げる仕組みにすれば、C側から動かすことができるからこれでいいかな？

タイミングの解決方法は勉強会の課題にしよう。

Tweet write: 2017/07/31/ 22:19:22