SDxのログ

SDxのRGBtoHSVサンプルでコンパイル状況を確認してみよう。

01:50:35 **** Build of configuration Debug for project Sample01 ****
make pre-build main-build 
sdsoc_make_clean Debug

Building file: ../src/top.cpp
Invoking: SDS++ Compiler
sds++ -Wall -O0 -g -I"../src" -c -fmessage-length=0 -MT"src/top.o" -MMD -MP -MF"src/top.d" -MT"src/top.o" -o "src/top.o" "../src/top.cpp" -sds-hw RgbToHsv top.cpp  -clkid 1 -sds-end -sds-sys-config linux -sds-proc a9_0 -sds-pf zybo
INFO: [SDSoC 0-0] Processing -sds-hw block for RgbToHsv
INFO: [SDSoC 0-0] Create data motion intermediate representation
INFO: [SDSoC 0-0] Performing accelerator source linting for RgbToHsv
INFO: [SDSoC 0-0] Performing pragma generation
INFO: [SDSoC 0-0] Successfully generated tcl script: /home/hidemi/workspace/SDSoC/Sample01/Debug/_sds/vhls/RgbToHsv.tcl
INFO: [SDSoC 0-0] Moving function RgbToHsv to Programmable Logic
sds++ log file saved as /home/hidemi/workspace/SDSoC/Sample01/Debug/_sds/reports/sds_top.log

Finished building: ../src/top.cpp

Building target: Sample01.elf
Invoking: SDS++ Linker
sds++  -o "Sample01.elf"  ./src/top.o    -dmclkid 1  -sds-sys-config linux -sds-proc a9_0 -sds-pf zybo
INFO: [SDSoC 0-0] Analyzing object files
... /home/hidemi/workspace/SDSoC/Sample01/Debug/src/top.o
INFO: [SDSoC 0-0] Generating data motion network
INFO: [SDSoC 0-0] Analyzing hardware accelerators...
INFO: [SDSoC 0-0] Analyzing callers to hardware accelerators...
INFO: [SDSoC 0-0] Scheduling data transfer graph for partition 0
INFO: [SDSoC 0-0] Creating data motion network hardware for partition 0
INFO: [SDSoC 0-0] Creating software stub functions for partition 0
INFO: [SDSoC 0-0] Generating data motion network report for partition 0
INFO: [SDSoC 0-0] Rewriting caller code
INFO: [SDSoC 0-0] Creating block diagram (BD), address map, port information and device registration for partition 0 (this may take a few minutes)
system_linker started at Sat Jan 14 01:51:34 JST 2017
INFO: [SDSoC 0-0] Copying address map
INFO: [SDSoC 0-0] Creating port and device registration data
system_linker completed at Sat Jan 14 01:53:27 JST 2017
INFO: [SDSoC 0-0] Rewrite caller functions
INFO: [SDSoC 0-0] Compile caller rewrite file /home/hidemi/workspace/SDSoC/Sample01/Debug/_sds/swstubs/top.cpp
INFO: [SDSoC 0-0] Prepare hardware access API functions
INFO: [SDSoC 0-0] Create accelerator stub functions
INFO: [SDSoC 0-0] Compile hardware access API functions
INFO: [SDSoC 0-0] Compile accelerator stub functions
INFO: [SDSoC 0-0] Link application ELF file
INFO: [SDSoC 0-0] Enable generation of hardware programming files
INFO: [SDSoC 0-0] Enable generation of boot files
INFO: [SDSoC 0-0] Calling system_linker for partition 0
system_linker started at Sat Jan 14 01:53:28 JST 2017
INFO: [SDSoC 0-0] Generating bitstream for platform zybo.
      This may take some time to complete
... [02:18:25] Starting synth_design
... [02:18:30] Starting RTL Elaboration : Time (s): cpu = 00:00:35 ; elapsed = 00:00:36 . Memory (MB): peak = 1335.480 ; gain = 423.492 ; free physical = 1208 ; free virtual = 5567
... [02:18:50] Start Loading Part and Timing Information
... [02:18:50] Start Applying 'set_property' XDC Constraints
... [02:18:50] Start RTL Component Statistics 
... [02:18:50] Start RTL Hierarchical Component Statistics 
... [02:18:50] Start Part Resource Summary
... [02:18:50] Start Cross Boundary and Area Optimization
... [02:18:50] Start Timing Optimization
... [02:19:06] Start Applying XDC Timing Constraints
... [02:19:06] Start Technology Mapping
... [02:19:06] Start IO Insertion
... [02:19:06] Start Flattening Before IO Insertion
... [02:19:06] Start Final Netlist Cleanup
... [02:19:06] Start Renaming Generated Instances
... [02:19:06] Start Rebuilding User Hierarchy
... [02:19:06] Start Renaming Generated Ports
... [02:19:06] Start Handling Custom Attributes
... [02:19:06] Start Renaming Generated Nets
... [02:19:06] Start Writing Synthesis Report
... [02:19:53] Starting DRC Task
... [02:19:53] Starting Logic Optimization Task
... [02:20:03] Starting Connectivity Check Task
... [02:20:03] Starting Power Optimization Task
... [02:20:08] Starting PowerOpt Patch Enables Task
... [02:20:18] Starting Placer Task
... [02:20:53] Starting Routing Task
INFO: [SDSoC 0-0] Creating boot files
system_linker completed at Sat Jan 14 02:22:15 JST 2017
All user specified timing constraints are met.
sds++ log file saved as /home/hidemi/workspace/SDSoC/Sample01/Debug/_sds/reports/sds.log

Finished building target: Sample01.elf

02:22:15 Build Finished (took 31m:39s.229ms)

1:50に開始して、2:22に終わりました。

かかった約30分です。

FPGAの論理合成や配置配線をしてていれば、これぐらいの時間がかかることは許容範囲(慣れ?)になってきますが、ソフトウェアのコンパイル時間と考えると非常に時間がかかっている。

これがなんとかなればねぇ〜。